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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb49bd977sm51923805e9.11.2025.10.10.08.51.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 10 Oct 2025 08:51:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Christoph Muellner , Heinrich Schuchardt , Palmer Dabbelt , Alistair Francis , Liu Zhiwei , Anton Johansson , Richard Henderson , Valentin Haudiquet , Weiwei Li , qemu-riscv@nongnu.org, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 04/13] target/riscv: Conceal MO_TE within gen_inc() Date: Fri, 10 Oct 2025 17:50:35 +0200 Message-ID: <20251010155045.78220-5-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251010155045.78220-1-philmd@linaro.org> References: <20251010155045.78220-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All callers of gen_inc() set the MO_TE flag. Set it once in the callee. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/insn_trans/trans_xthead.c.inc | 34 ++++++++++++---------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 754cb80e221..7e69906e5bf 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -568,6 +568,7 @@ static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, TCGv rd = dest_gpr(ctx, a->rd); TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); + memop |= MO_TE; tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rd, rd); @@ -588,6 +589,7 @@ static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, TCGv data = get_gpr(ctx, a->rd, EXT_NONE); TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); + memop |= MO_TE; tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rs1, rs1); @@ -598,64 +600,64 @@ static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SQ, false); + return gen_load_inc(ctx, a, MO_SQ, false); } static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SQ, true); + return gen_load_inc(ctx, a, MO_SQ, true); } static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SL, false); + return gen_load_inc(ctx, a, MO_SL, false); } static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SL, true); + return gen_load_inc(ctx, a, MO_SL, true); } static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UL, false); + return gen_load_inc(ctx, a, MO_UL, false); } static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UL, true); + return gen_load_inc(ctx, a, MO_UL, true); } static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SW, false); + return gen_load_inc(ctx, a, MO_SW, false); } static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_SW, true); + return gen_load_inc(ctx, a, MO_SW, true); } static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UW, false); + return gen_load_inc(ctx, a, MO_UW, false); } static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_load_inc(ctx, a, MO_TE | MO_UW, true); + return gen_load_inc(ctx, a, MO_UW, true); } static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) @@ -686,38 +688,38 @@ static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SQ, false); + return gen_store_inc(ctx, a, MO_SQ, false); } static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); REQUIRE_64BIT(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SQ, true); + return gen_store_inc(ctx, a, MO_SQ, true); } static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SL, false); + return gen_store_inc(ctx, a, MO_SL, false); } static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SL, true); + return gen_store_inc(ctx, a, MO_SL, true); } static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SW, false); + return gen_store_inc(ctx, a, MO_SW, false); } static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) { REQUIRE_XTHEADMEMIDX(ctx); - return gen_store_inc(ctx, a, MO_TE | MO_SW, true); + return gen_store_inc(ctx, a, MO_SW, true); } static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) -- 2.51.0