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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7992dd7ee5bsm3764830b3a.85.2025.10.10.13.19.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Oct 2025 13:19:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 3/7] target/arm: Add AIE to ARMVAParameters Date: Fri, 10 Oct 2025 13:19:13 -0700 Message-ID: <20251010201917.685716-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251010201917.685716-1-richard.henderson@linaro.org> References: <20251010201917.685716-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Allow the bit to be set in TCR2; extract the bit in aa64_va_parameters. Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/helper.c | 30 +++++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f539bbe58e..a65386aaed 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1391,6 +1391,7 @@ typedef struct ARMVAParameters { bool hd : 1; ARMGranuleSize gran : 2; bool pie : 1; + bool aie : 1; } ARMVAParameters; /** diff --git a/target/arm/helper.c b/target/arm/helper.c index e4d1651440..8c0b8889db 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6098,6 +6098,9 @@ static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, if (cpu_isar_feature(aa64_s1pie, cpu)) { valid_mask |= TCR2_PIE; } + if (cpu_isar_feature(aa64_aie, cpu)) { + valid_mask |= TCR2_AIE; + } value &= valid_mask; raw_write(env, ri, value); } @@ -6111,7 +6114,10 @@ static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, if (cpu_isar_feature(aa64_s1pie, cpu)) { valid_mask |= TCR2_PIE; } - if (cpu_isar_feature(aa64_mec, env_archcpu(env))) { + if (cpu_isar_feature(aa64_aie, cpu)) { + valid_mask |= TCR2_AIE; + } + if (cpu_isar_feature(aa64_mec, cpu)) { valid_mask |= TCR2_AMEC0 | TCR2_AMEC1; } value &= valid_mask; @@ -9666,6 +9672,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, { uint64_t tcr = regime_tcr(env, mmu_idx); bool epd, hpd, tsz_oob, ds, ha, hd, pie = false; + bool aie = false; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMGranuleSize gran; ARMCPU *cpu = env_archcpu(env); @@ -9688,10 +9695,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, if (r_el == 3) { pie = (extract64(tcr, 35, 1) && cpu_isar_feature(aa64_s1pie, cpu)); - } else { - pie = ((env->cp15.tcr2_el[2] & TCR2_PIE) - && (!arm_feature(env, ARM_FEATURE_EL3) - || (env->cp15.scr_el3 & SCR_TCR2EN))); + aie = (extract64(tcr, 37, 1) + && cpu_isar_feature(aa64_aie, cpu)); + } else if (!arm_feature(env, ARM_FEATURE_EL3) + || (env->cp15.scr_el3 & SCR_TCR2EN)) { + pie = env->cp15.tcr2_el[2] & TCR2_PIE; + aie = env->cp15.tcr2_el[2] & TCR2_AIE; } } epd = false; @@ -9733,10 +9742,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, epd = true; } - pie = ((env->cp15.tcr2_el[r_el] & TCR2_PIE) - && (!arm_feature(env, ARM_FEATURE_EL3) - || (env->cp15.scr_el3 & SCR_TCR2EN)) - && (r_el == 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN))); + if ((!arm_feature(env, ARM_FEATURE_EL3) + || (env->cp15.scr_el3 & SCR_TCR2EN)) + && (r_el == 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN))) { + pie = env->cp15.tcr2_el[r_el] & TCR2_PIE; + aie = env->cp15.tcr2_el[r_el] & TCR2_AIE; + } } hpd |= pie; @@ -9818,6 +9829,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, .hd = ha && hd, .gran = gran, .pie = pie, + .aie = aie, }; } -- 2.43.0