From: Zejun Zhao <jelly.zhao.42@gmail.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
qemu-devel@nongnu.org
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Weiwei Li <liwei1518@gmail.com>,
Liu Zhiwei <zhiwei_liu@linux.alibaba.com>,
qemu-riscv@nongnu.org, Max Chou <max.chou@sifive.com>
Subject: Re: [PATCH] hw/riscv: Correct mmu-type property of sifive_u harts in device tree
Date: Mon, 13 Oct 2025 23:43:35 +0800 [thread overview]
Message-ID: <20251013154340.1989427-1-jelly.zhao.42@gmail.com> (raw)
In-Reply-To: <cca1b0f7-8063-4d53-88f7-a56eb56b3eca@ventanamicro.com>
On Mon, 13 Oct 2025 11:38:48 -0300, Daniel wrote:
> But the documentation I found [1] seems to indicate that it should
> support sv48.
The second paragraph after the referenced Table 9 from [1] states:
> For RV64 architectures on SiFive designs,satp.MODE=8 is used for Sv39
> virtual addressing, and no other modes are currently supported.
And here is the same statement from [1]:
> The U5 has support for virtual memory through the use of a Memory
> Management Unit (MMU). The MMU supports the Bare and Sv39 modes as
> described inThe RISC‑V Instruction Set Man-ual, Volume II: Privileged
> Architecture, Version 1.10.
So I believe we should not try to support Sv48 for this hart. Hardcoding
it to Sv39 should be fine and correct.
Regards,
Zejun
[1] https://starfivetech.com/uploads/u54_core_complex_manual_21G1.pdf
next prev parent reply other threads:[~2025-10-13 15:44 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-13 13:32 [PATCH] hw/riscv: Correct mmu-type property of sifive_u harts in device tree Zejun Zhao
2025-10-13 14:38 ` Daniel Henrique Barboza
2025-10-13 15:43 ` Zejun Zhao [this message]
2025-10-13 16:16 ` Daniel Henrique Barboza
2025-10-13 16:16 ` Daniel Henrique Barboza
2025-10-15 2:31 ` Alistair Francis
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