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Tsirkin" To: Sairaj Kodilkar Cc: qemu-devel@nongnu.org, alejandro.j.jimenez@oracle.com, pbonzini@redhat.com, richard.henderson@linaro.org, philmd@linaro.org, suravee.suthikulpanit@amd.com, vasant.hegde@amd.com, marcel.apfelbaum@gmail.com, eduardo@habkost.net, aik@amd.com Subject: Re: [PATCH v2 2/2] amd_iommu: Support 64 bit address for IOTLB lookup Message-ID: <20251014050512-mutt-send-email-mst@kernel.org> References: <20251013050046.393-1-sarunkod@amd.com> <20251013050046.393-3-sarunkod@amd.com> <20251013041617-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On Tue, Oct 14, 2025 at 02:34:28PM +0530, Sairaj Kodilkar wrote: > > > On 10/13/2025 1:49 PM, Michael S. Tsirkin wrote: > > On Mon, Oct 13, 2025 at 10:30:46AM +0530, Sairaj Kodilkar wrote: > > > Physical AMD IOMMU supports up to 64 bits of DMA address. When device tries > > > to read or write from a given DMA address, IOMMU translates the address > > > using page table assigned to that device. Since IOMMU uses per device page > > > tables, the emulated IOMMU should use the cache tag of 68 bits > > > (64 bit address - 12 bit page alignment + 16 bit device ID). > > > > > > Current emulated AMD IOMMU uses GLib hash table to create software iotlb > > > and uses 64 bit key to store the IOVA and deviceID, which limits the IOVA > > > to 60 bits. This causes failure while setting up the device when guest is > > > booted with "iommu.forcedac=1". > > > > > > To solve this problem, Use 64 bit IOVA and 16 bit devid as key to store > > > entries in IOTLB; Use upper 52 bits of IOVA (GFN) and lower 12 bits of > > > the device ID to construct the 64 bit hash key in order avoid the > > > truncation as much as possible (reducing hash collisions). > > > > > > Fixes: d29a09ca6842 ("hw/i386: Introduce AMD IOMMU") > > > Signed-off-by: Sairaj Kodilkar > > I am wondering whether we need to limit how much host memory > > can the shadow take. Because with so many bits, the sky is the limit ... > > OTOH it's not directly caused by this patch, but it's something > > we should think about maybe. > > I don't think I fully understand this. Do you mean the host memory > taken by the pages used to build shadow page table ? the memory used by the hash table. > > > Something more to improve: > > > > > > > --- > > > hw/i386/amd_iommu.c | 57 ++++++++++++++++++++++++++++++--------------- > > > hw/i386/amd_iommu.h | 4 ++-- > > > 2 files changed, 40 insertions(+), 21 deletions(-) > > > > > > diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c > > > index b194e3294dd7..a218d147e53d 100644 > > > --- a/hw/i386/amd_iommu.c > > > +++ b/hw/i386/amd_iommu.c > > > @@ -106,6 +106,11 @@ typedef struct amdvi_as_key { > > > uint8_t devfn; > > > } amdvi_as_key; > > > +typedef struct amdvi_iotlb_key { > > > + uint64_t gfn; > > > + uint16_t devid; > > > +} amdvi_iotlb_key; > > > + > > Pls change struct and typedef names to match qemu coding style. > Thanks > Sairaj