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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-46fb479c171sm249133035e9.0.2025.10.14.10.39.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 14 Oct 2025 10:39:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , qemu-ppc@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson Subject: [PATCH 3/3] buildsys: Remove support for 32-bit PPC hosts Date: Tue, 14 Oct 2025 19:38:59 +0200 Message-ID: <20251014173900.87497-4-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251014173900.87497-1-philmd@linaro.org> References: <20251014173900.87497-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=philmd@linaro.org; helo=mail-wm1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Stop detecting 32-bit PPC host as supported. See previous commit for rationale. Signed-off-by: Philippe Mathieu-Daudé --- configure | 12 ++---------- include/qemu/host-utils.h | 2 +- include/qemu/timer.h | 13 +------------ disas/disas-host.c | 4 +--- util/cacheflush.c | 4 ++-- 5 files changed, 7 insertions(+), 28 deletions(-) diff --git a/configure b/configure index ce76a00aff1..8205c8df599 100755 --- a/configure +++ b/configure @@ -391,15 +391,12 @@ elif check_define __sparc__ ; then else cpu="sparc" fi -elif check_define _ARCH_PPC ; then - if check_define _ARCH_PPC64 ; then +elif check_define _ARCH_PPC64 ; then if check_define _LITTLE_ENDIAN ; then cpu="ppc64le" else cpu="ppc64" fi - else - cpu="ppc" fi elif check_define __mips__ ; then if check_define __mips64 ; then @@ -479,11 +476,6 @@ case "$cpu" in linux_arch=mips ;; - ppc) - host_arch=ppc - linux_arch=powerpc - CPU_CFLAGS="-m32" - ;; ppc64) host_arch=ppc64 linux_arch=powerpc @@ -1477,7 +1469,7 @@ probe_target_compiler() { container_image=debian-all-test-cross container_cross_prefix=mips64-linux-gnuabi64- ;; - ppc|ppc64|ppc64le) + ppc64|ppc64le) container_image=debian-all-test-cross container_cross_prefix=powerpc${target_arch#ppc}-linux-gnu- ;; diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index dd558589cb5..22d440287f1 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -806,7 +806,7 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t n1, asm("dlgr %0, %1" : "+r"(n) : "r"(d)); *r = n >> 64; return n; -#elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7) +#elif defined(_ARCH_PWR7) /* From Power ISA 2.06, programming note for divdeu. */ uint64_t q1, q2, Q, r1, r2, R; asm("divdeu %0,%2,%4; divdu %1,%3,%4" diff --git a/include/qemu/timer.h b/include/qemu/timer.h index abd2204f3be..6c15acebbc0 100644 --- a/include/qemu/timer.h +++ b/include/qemu/timer.h @@ -850,12 +850,11 @@ static inline int64_t get_clock(void) /*******************************************/ /* host CPU ticks (if available) */ -#if defined(_ARCH_PPC) +#if defined(_ARCH_PPC64) static inline int64_t cpu_get_host_ticks(void) { int64_t retval; -#ifdef _ARCH_PPC64 /* This reads timebase in one 64bit go and includes Cell workaround from: http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html */ @@ -863,16 +862,6 @@ static inline int64_t cpu_get_host_ticks(void) "cmpwi %0,0\n\t" "beq- $-8" : "=r" (retval)); -#else - /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */ - unsigned long junk; - __asm__ __volatile__ ("mfspr %1,269\n\t" /* mftbu */ - "mfspr %L0,268\n\t" /* mftb */ - "mfspr %0,269\n\t" /* mftbu */ - "cmpw %0,%1\n\t" - "bne $-16" - : "=r" (retval), "=r" (junk)); -#endif return retval; } diff --git a/disas/disas-host.c b/disas/disas-host.c index 8146fafe804..4b06f41fa6c 100644 --- a/disas/disas-host.c +++ b/disas/disas-host.c @@ -56,11 +56,9 @@ static void initialize_debug_host(CPUDebug *s) s->info.cap_mode = CS_MODE_64; s->info.cap_insn_unit = 1; s->info.cap_insn_split = 8; -#elif defined(_ARCH_PPC) +#elif defined(_ARCH_PPC64) s->info.cap_arch = CS_ARCH_PPC; -# ifdef _ARCH_PPC64 s->info.cap_mode = CS_MODE_64; -# endif #elif defined(__riscv) #if defined(_ILP32) || (__riscv_xlen == 32) s->info.print_insn = print_insn_riscv32; diff --git a/util/cacheflush.c b/util/cacheflush.c index 17c58918de6..69c9614e2c9 100644 --- a/util/cacheflush.c +++ b/util/cacheflush.c @@ -153,7 +153,7 @@ static void arch_cache_info(int *isize, int *dsize) } } -#elif defined(_ARCH_PPC) && defined(__linux__) +#elif defined(_ARCH_PPC64) && defined(__linux__) # include "elf.h" static void arch_cache_info(int *isize, int *dsize) @@ -187,7 +187,7 @@ static void fallback_cache_info(int *isize, int *dsize) } else if (*dsize) { *isize = *dsize; } else { -#if defined(_ARCH_PPC) +#if defined(_ARCH_PPC64) /* * For PPC, we're going to use the cache sizes computed for * flush_idcache_range. Which means that we must use the -- 2.51.0