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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f93ea2sm172100975ad.126.2025.10.14.13.07.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 13:07:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 11/37] target/arm: Handle ARM_CP_128BIT in cpu reset Date: Tue, 14 Oct 2025 13:06:52 -0700 Message-ID: <20251014200718.422022-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org> References: <20251014200718.422022-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Richard Henderson --- target/arm/cpu.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2fc17eab6..000fa20bc6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -180,7 +180,7 @@ static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque) ARMCPRegInfo *ri = value; ARMCPU *cpu = opaque; - if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_128BIT)) { return; } @@ -208,16 +208,24 @@ static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque) */ ARMCPRegInfo *ri = value; ARMCPU *cpu = opaque; - uint64_t oldvalue, newvalue; if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { return; } + if (ri->type & ARM_CP_128BIT) { + /* + * All 128-bit registers are UNKNOWN at reset. + * For qemu, they are all cleared by memset to end_reset_fields. + */ + assert(!int128_nz(read_raw_cp_reg128(&cpu->env, ri))); + } else { + uint64_t oldvalue, newvalue; - oldvalue = read_raw_cp_reg(&cpu->env, ri); - cp_reg_reset(key, value, opaque); - newvalue = read_raw_cp_reg(&cpu->env, ri); - assert(oldvalue == newvalue); + oldvalue = read_raw_cp_reg(&cpu->env, ri); + cp_reg_reset(key, value, opaque); + newvalue = read_raw_cp_reg(&cpu->env, ri); + assert(oldvalue == newvalue); + } } static void arm_cpu_reset_hold(Object *obj, ResetType type) -- 2.43.0