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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f93ea2sm172100975ad.126.2025.10.14.13.07.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 13:07:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 21/37] target/arm: Extend PAR_EL1 to 128-bit Date: Tue, 14 Oct 2025 13:07:02 -0700 Message-ID: <20251014200718.422022-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org> References: <20251014200718.422022-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Do not yet produce the 128-bit AT format result, but zero the high bits whenever the low bits are written. This corresponds to PAR_EL1.D128 = 0, and bits [127:65] as RES0. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++++- target/arm/internals.h | 1 + target/arm/helper.c | 18 +++++++++++++++++- target/arm/tcg/cpregs-at.c | 4 ++++ 4 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a030539488..e03d832717 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -429,7 +429,8 @@ typedef struct CPUArchState { }; uint64_t hpfar_el2; uint64_t hstr_el2; - union { /* Translation result. */ + /* Translation result. */ + union { struct { uint64_t _unused_par_0; uint64_t par_ns; @@ -438,6 +439,7 @@ typedef struct CPUArchState { }; uint64_t par_el[4]; }; + uint64_t par_el1_hi; /* high 64 bits of 128-bit PAR_EL1 */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; @@ -1750,6 +1752,7 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) #define SCR_SCTLR2EN (1ULL << 44) #define SCR_PIEN (1ULL << 45) #define SCR_AIEN (1ULL << 46) +#define SCR_D128EN (1ULL << 47) #define SCR_GPF (1ULL << 48) #define SCR_MECEN (1ULL << 49) #define SCR_NSE (1ULL << 62) diff --git a/target/arm/internals.h b/target/arm/internals.h index a65386aaed..bda2400b65 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -251,6 +251,7 @@ FIELD(VSTCR, SA, 30, 1) #define HCRX_MSCEN (1ULL << 11) #define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) +#define HCRX_D128EN (1ULL << 17) #define HCRX_GCSEN (1ULL << 22) #define HPFAR_NS (1ULL << 63) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7800d83f48..f9a2a7d62d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -508,6 +508,20 @@ static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static CPAccessResult access_d128(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el = arm_current_el(env); + + if (el <= 1 && !(arm_hcrx_el2_eff(env) & HCRX_D128EN)) { + return CP_ACCESS_TRAP_EL2; + } + if (el <= 2 && !(env->cp15.scr_el3 & SCR_D128EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); @@ -3279,7 +3293,9 @@ static void define_par_register(ARMCPU *cpu) .name = "PAR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0, .access = PL1_RW, .fgt = FGT_PAR_EL1, - .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]) + .type = ARM_CP_128BIT, .access128fn = access_d128, + .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]), + .fieldoffsethi = offsetof(CPUARMState, cp15.par_el1_hi), }; static ARMCPRegInfo par64_reginfo[2] = { diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index 0e8f229aa7..9e6af3d974 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -353,6 +353,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, ss = for_el3 ? arm_security_space(env) : arm_security_space_below_el3(env); env->cp15.par_el[1] = do_ats_write(env, value, access_perm, mmu_idx, ss); + env->cp15.par_el1_hi = 0; } static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -496,6 +497,7 @@ static void ats_s1e1a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) ARMSecuritySpace ss = arm_security_space_below_el3(env); env->cp15.par_el[1] = do_ats_write(env, value, 0, mmu_idx, ss); + env->cp15.par_el1_hi = 0; } static void ats_s1e2a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) @@ -505,12 +507,14 @@ static void ats_s1e2a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) ARMSecuritySpace ss = arm_security_space_below_el3(env); env->cp15.par_el[1] = do_ats_write(env, value, 0, mmu_idx, ss); + env->cp15.par_el1_hi = 0; } static void ats_s1e3a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { env->cp15.par_el[1] = do_ats_write(env, value, 0, ARMMMUIdx_E3, arm_security_space(env)); + env->cp15.par_el1_hi = 0; } static const ARMCPRegInfo ats1a_reginfo[] = { -- 2.43.0