From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v2 25/37] target/arm: Extend TTBR system registers to 128-bit
Date: Tue, 14 Oct 2025 13:07:06 -0700 [thread overview]
Message-ID: <20251014200718.422022-26-richard.henderson@linaro.org> (raw)
In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org>
So far, just extend the data type and check access; do not yet
consume the 128-bit table format.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 9 +++--
target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++---------
2 files changed, 74 insertions(+), 18 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e03d832717..65037f1dd3 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -344,7 +344,8 @@ typedef struct CPUArchState {
uint64_t cptr_el[4]; /* ARMv8 feature trap registers */
uint64_t sder; /* Secure debug enable register. */
uint32_t nsacr; /* Non-secure access control register. */
- union { /* MMU translation table base 0. */
+ /* MMU translation table bases. */
+ union {
struct {
uint64_t _unused_ttbr0_0;
uint64_t ttbr0_ns;
@@ -353,7 +354,7 @@ typedef struct CPUArchState {
};
uint64_t ttbr0_el[4];
};
- union { /* MMU translation table base 1. */
+ union {
struct {
uint64_t _unused_ttbr1_0;
uint64_t ttbr1_ns;
@@ -364,6 +365,10 @@ typedef struct CPUArchState {
};
uint64_t vttbr_el2; /* Virtualization Translation Table Base. */
uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */
+ /* High 64 bits of 128-bit Translation Table Bases. */
+ uint64_t ttbr0_el_hi[4];
+ uint64_t ttbr1_el_hi[4];
+ uint64_t vttbr_el2_hi;
/* MMU translation table base control. */
uint64_t tcr_el[4];
uint64_t tcr2_el[3];
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 2b55e219c2..90a940aeb9 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -108,10 +108,6 @@ void raw_write128(CPUARMState *env, const ARMCPRegInfo *ri,
CPREG_FIELD128_H64(env, ri) = valuehi;
}
-#undef CPREG_FIELD32
-#undef CPREG_FIELD64
-#undef CPREG_FIELD128_H64
-
static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
{
return (char *)env + ri->fieldoffset;
@@ -522,6 +518,16 @@ static CPAccessResult access_d128(CPUARMState *env, const ARMCPRegInfo *ri,
return CP_ACCESS_OK;
}
+static CPAccessResult access_tvm_trvm_d128(CPUARMState *env,
+ const ARMCPRegInfo *ri, bool isread)
+{
+ CPAccessResult ret = access_tvm_trvm(env, ri, isread);
+ if (ret == CP_ACCESS_OK) {
+ ret = access_d128(env, ri, isread);
+ }
+ return ret;
+}
+
static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = env_archcpu(env);
@@ -2932,7 +2938,7 @@ static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void flush_if_asid_change(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t new, unsigned mask)
{
- uint64_t old = raw_read(env, ri);
+ uint64_t old = CPREG_FIELD64(env, ri);
/* The ASID or VMID is in bits [63:48]. */
if ((old ^ new) >> 48) {
@@ -2961,6 +2967,16 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
raw_write(env, ri, value);
}
+static void vmsa_ttbr_write128(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t vallo, uint64_t valhi)
+{
+ flush_if_asid_change(env, ri, vallo,
+ ARMMMUIdxBit_E10_1 |
+ ARMMMUIdxBit_E10_1_PAN |
+ ARMMMUIdxBit_E10_0);
+ raw_write128(env, ri, vallo, valhi);
+}
+
static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -2981,6 +2997,18 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
raw_write(env, ri, value);
}
+static void vmsa_tcr_ttbr_el2_write128(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t vallo, uint64_t valhi)
+{
+ if (arm_hcr_el2_eff(env) & HCR_E2H) {
+ flush_if_asid_change(env, ri, vallo,
+ ARMMMUIdxBit_E20_2 |
+ ARMMMUIdxBit_E20_2_PAN |
+ ARMMMUIdxBit_E20_0);
+ }
+ raw_write128(env, ri, vallo, valhi);
+}
+
static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -2992,6 +3020,13 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
raw_write(env, ri, value);
}
+static void vttbr_write128(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t vallo, uint64_t valhi)
+{
+ flush_if_asid_change(env, ri, vallo, alle1_tlbmask(env));
+ raw_write128(env, ri, vallo, valhi);
+}
+
static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
{ .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS,
@@ -3339,26 +3374,35 @@ static void define_ttbr_registers(ARMCPU *cpu)
{ .name = "TTBR0_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
.access = PL1_RW, .accessfn = access_tvm_trvm,
- .fgt = FGT_TTBR0_EL1,
+ .access128fn = access_tvm_trvm_d128,
+ .fgt = FGT_TTBR0_EL1, .type = ARM_CP_128BIT,
.nv2_redirect_offset = 0x200 | NV2_REDIR_NV1,
.vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 0, 0),
.vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 0, 0),
.writefn = vmsa_ttbr_write, .raw_writefn = raw_write,
- .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[1]) },
+ .write128fn = vmsa_ttbr_write128, .raw_write128fn = raw_write128,
+ .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[1]),
+ .fieldoffsethi = offsetof(CPUARMState, cp15.ttbr0_el_hi[1]) },
{ .name = "TTBR1_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
.access = PL1_RW, .accessfn = access_tvm_trvm,
- .fgt = FGT_TTBR1_EL1,
+ .access128fn = access_tvm_trvm_d128,
+ .fgt = FGT_TTBR1_EL1, .type = ARM_CP_128BIT,
.nv2_redirect_offset = 0x210 | NV2_REDIR_NV1,
.vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 0, 1),
.vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 0, 1),
.writefn = vmsa_ttbr_write, .raw_writefn = raw_write,
- .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[1]) },
+ .write128fn = vmsa_ttbr_write128, .raw_write128fn = raw_write128,
+ .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[1]),
+ .fieldoffsethi = offsetof(CPUARMState, cp15.ttbr1_el_hi[1]) },
{ .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .resetvalue = 0,
+ .access = PL2_RW, .access128fn = access_d128, .type = ARM_CP_128BIT,
.writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write,
- .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
+ .write128fn = vmsa_tcr_ttbr_el2_write128,
+ .raw_write128fn = raw_write128,
+ .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]),
+ .fieldoffsethi = offsetof(CPUARMState, cp15.ttbr0_el_hi[2]) },
{ .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
.access = PL3_RW, .resetvalue = 0,
@@ -4548,9 +4592,13 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.writefn = vttbr_write, .raw_writefn = raw_write },
{ .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
- .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write,
+ .type = ARM_CP_128BIT,
+ .access = PL2_RW, .access128fn = access_d128,
+ .writefn = vttbr_write, .raw_writefn = raw_write,
+ .write128fn = vttbr_write128, .raw_write128fn = raw_write128,
.nv2_redirect_offset = 0x20,
- .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
+ .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
+ .fieldoffsethi = offsetof(CPUARMState, cp15.vttbr_el2_hi) },
{ .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
.access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
@@ -6196,9 +6244,12 @@ static const ARMCPRegInfo contextidr_el2 = {
static const ARMCPRegInfo vhe_reginfo[] = {
{ .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
- .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
- .raw_writefn = raw_write,
- .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
+ .type = ARM_CP_128BIT,
+ .access = PL2_RW, .access128fn = access_d128,
+ .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write,
+ .write128fn = vmsa_tcr_ttbr_el2_write128, .raw_write128fn = raw_write128,
+ .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]),
+ .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el_hi[2]) },
#ifndef CONFIG_USER_ONLY
{ .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2,
--
2.43.0
next prev parent reply other threads:[~2025-10-14 20:14 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-14 20:06 [PATCH v2 00/37] target/arm: Implement FEAT_SYSREG128 Richard Henderson
2025-10-14 20:06 ` [PATCH v2 01/37] target/arm: Implement isar tests for FEAT_SYSREG128, FEAT_SYSINSTR128 Richard Henderson
2025-10-17 12:34 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 02/37] target/arm: Define CP_REG_SIZE_U128 Richard Henderson
2025-10-17 12:37 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 03/37] target/arm: Update ARMCPRegInfo for 128-bit sysregs Richard Henderson
2025-10-17 12:56 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 04/37] target/arm: Asserts for ARM_CP_128BIT in define_one_arm_cp_reg Richard Henderson
2025-10-17 12:59 ` Peter Maydell
2025-10-17 15:01 ` Richard Henderson
2025-10-14 20:06 ` [PATCH v2 05/37] target/arm: Split add_cpreg_to_hashtable_aa64 Richard Henderson
2025-10-17 13:05 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 06/37] target/arm: Add raw_read128, raw_write128 Richard Henderson
2025-10-17 13:07 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 07/37] target/arm: Add read_raw_cp_reg128, write_raw_cp_reg128 Richard Henderson
2025-10-17 13:11 ` Peter Maydell
2025-10-17 15:04 ` Richard Henderson
2025-10-20 13:23 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 08/37] target/arm: Use cpreg_field_type in arm_gen_one_feature_sysreg Richard Henderson
2025-10-17 13:14 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 09/37] target/arm: Merge arm_gen_one_feature_sysreg into the single caller Richard Henderson
2025-10-17 13:16 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 10/37] target/arm: Handle MO_128 in arm_gdb_get_sysreg Richard Henderson
2025-10-17 13:18 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 11/37] target/arm: Handle ARM_CP_128BIT in cpu reset Richard Henderson
2025-10-17 13:34 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 12/37] target/arm: Put 128-bit sysregs into a separate list Richard Henderson
2025-10-20 12:34 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 13/37] target/arm/kvm: Assert no 128-bit sysregs in kvm_arm_init_cpreg_list Richard Henderson
2025-10-20 12:34 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 14/37] target/arm/hvf: Assert no 128-bit sysregs in hvf_arch_init_vcpu Richard Henderson
2025-10-20 12:35 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 15/37] migration: Add vmstate_info_int128 Richard Henderson
2025-10-20 12:41 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 16/37] target/arm: Migrate cpreg128 registers Richard Henderson
2025-10-20 12:44 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 17/37] target/arm: Add syn_aa64_sysreg128trap Richard Henderson
2025-10-20 12:45 ` Peter Maydell
2025-10-14 20:06 ` [PATCH v2 18/37] target/arm: Introduce helper_{get,set}_cp_reg128 Richard Henderson
2025-10-20 12:49 ` [PATCH v2 18/37] target/arm: Introduce helper_{get, set}_cp_reg128 Peter Maydell
2025-10-14 20:07 ` [PATCH v2 19/37] target/arm: Implement MRRS, MSRR, SYSP Richard Henderson
2025-10-20 13:15 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 20/37] target/arm: Consolidate definitions of PAR Richard Henderson
2025-10-20 13:31 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 21/37] target/arm: Extend PAR_EL1 to 128-bit Richard Henderson
2025-10-17 12:49 ` Peter Maydell
2025-10-17 19:03 ` Richard Henderson
2025-10-14 20:07 ` [PATCH v2 22/37] target/arm: Consolidate definitions of TTBR[01] Richard Henderson
2025-10-20 14:00 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 23/37] target/arm: Split out flush_if_asid_change Richard Henderson
2025-10-20 14:02 ` Peter Maydell
2025-10-20 14:12 ` Philippe Mathieu-Daudé
2025-10-14 20:07 ` [PATCH v2 24/37] target/arm: Use flush_if_asid_change in vmsa_ttbr_write Richard Henderson
2025-10-20 14:08 ` Peter Maydell
2025-10-14 20:07 ` Richard Henderson [this message]
2025-10-20 14:14 ` [PATCH v2 25/37] target/arm: Extend TTBR system registers to 128-bit Peter Maydell
2025-10-14 20:07 ` [PATCH v2 26/37] target/arm: Implement TLBIP IPAS2E1, IPAS2LE1 Richard Henderson
2025-10-20 14:34 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 27/37] target/arm: Implement TLBIP IPAS2E1IS, IPAS2LE1IS Richard Henderson
2025-10-20 14:35 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 28/37] target/arm: Implement TLBIP RVAE1, RVAAE1, RVALE1, RVAALE1 Richard Henderson
2025-10-20 14:48 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 29/37] target/arm: Implement TLBIP RIPAS1E1, RIPAS1LE1, RIPAS2E1IS, RIPAS2LE1IS Richard Henderson
2025-10-20 14:49 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 30/37] target/arm: Implement TLBIP RVA{L}E2{IS,OS} Richard Henderson
2025-10-20 14:50 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 31/37] target/arm: Implement TLBIP RVA{L}E3{IS,OS} Richard Henderson
2025-10-20 14:50 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 32/37] target/arm: Implement TLBIP VA{L}E1{IS,OS} Richard Henderson
2025-10-20 14:52 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 33/37] target/arm: Implement TLBIP VAE2, VALE2 Richard Henderson
2025-10-20 14:52 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 34/37] target/arm: Implement TLBIP VAE3, VALE3 Richard Henderson
2025-10-20 14:52 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 35/37] target/arm: Implement TLBIP VA{L}E2{IS,OS} Richard Henderson
2025-10-20 14:53 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 36/37] target/arm: Implement TLBIP VA{L}E3{IS,OS} Richard Henderson
2025-10-20 14:53 ` Peter Maydell
2025-10-14 20:07 ` [PATCH v2 37/37] NOTFORMERGE: Enable FEAT_SYSREG128, FEAT_SYSINSTR128 for cpu max Richard Henderson
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