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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29034f93ea2sm172100975ad.126.2025.10.14.13.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Oct 2025 13:07:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 25/37] target/arm: Extend TTBR system registers to 128-bit Date: Tue, 14 Oct 2025 13:07:06 -0700 Message-ID: <20251014200718.422022-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251014200718.422022-1-richard.henderson@linaro.org> References: <20251014200718.422022-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org So far, just extend the data type and check access; do not yet consume the 128-bit table format. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 9 +++-- target/arm/helper.c | 83 ++++++++++++++++++++++++++++++++++++--------- 2 files changed, 74 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e03d832717..65037f1dd3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -344,7 +344,8 @@ typedef struct CPUArchState { uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ uint64_t sder; /* Secure debug enable register. */ uint32_t nsacr; /* Non-secure access control register. */ - union { /* MMU translation table base 0. */ + /* MMU translation table bases. */ + union { struct { uint64_t _unused_ttbr0_0; uint64_t ttbr0_ns; @@ -353,7 +354,7 @@ typedef struct CPUArchState { }; uint64_t ttbr0_el[4]; }; - union { /* MMU translation table base 1. */ + union { struct { uint64_t _unused_ttbr1_0; uint64_t ttbr1_ns; @@ -364,6 +365,10 @@ typedef struct CPUArchState { }; uint64_t vttbr_el2; /* Virtualization Translation Table Base. */ uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ + /* High 64 bits of 128-bit Translation Table Bases. */ + uint64_t ttbr0_el_hi[4]; + uint64_t ttbr1_el_hi[4]; + uint64_t vttbr_el2_hi; /* MMU translation table base control. */ uint64_t tcr_el[4]; uint64_t tcr2_el[3]; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2b55e219c2..90a940aeb9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -108,10 +108,6 @@ void raw_write128(CPUARMState *env, const ARMCPRegInfo *ri, CPREG_FIELD128_H64(env, ri) = valuehi; } -#undef CPREG_FIELD32 -#undef CPREG_FIELD64 -#undef CPREG_FIELD128_H64 - static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri) { return (char *)env + ri->fieldoffset; @@ -522,6 +518,16 @@ static CPAccessResult access_d128(CPUARMState *env, const ARMCPRegInfo *ri, return CP_ACCESS_OK; } +static CPAccessResult access_tvm_trvm_d128(CPUARMState *env, + const ARMCPRegInfo *ri, bool isread) +{ + CPAccessResult ret = access_tvm_trvm(env, ri, isread); + if (ret == CP_ACCESS_OK) { + ret = access_d128(env, ri, isread); + } + return ret; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { ARMCPU *cpu = env_archcpu(env); @@ -2932,7 +2938,7 @@ static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri, static void flush_if_asid_change(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t new, unsigned mask) { - uint64_t old = raw_read(env, ri); + uint64_t old = CPREG_FIELD64(env, ri); /* The ASID or VMID is in bits [63:48]. */ if ((old ^ new) >> 48) { @@ -2961,6 +2967,16 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } +static void vmsa_ttbr_write128(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t vallo, uint64_t valhi) +{ + flush_if_asid_change(env, ri, vallo, + ARMMMUIdxBit_E10_1 | + ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_0); + raw_write128(env, ri, vallo, valhi); +} + static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2981,6 +2997,18 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } +static void vmsa_tcr_ttbr_el2_write128(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t vallo, uint64_t valhi) +{ + if (arm_hcr_el2_eff(env) & HCR_E2H) { + flush_if_asid_change(env, ri, vallo, + ARMMMUIdxBit_E20_2 | + ARMMMUIdxBit_E20_2_PAN | + ARMMMUIdxBit_E20_0); + } + raw_write128(env, ri, vallo, valhi); +} + static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2992,6 +3020,13 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, raw_write(env, ri, value); } +static void vttbr_write128(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t vallo, uint64_t valhi) +{ + flush_if_asid_change(env, ri, vallo, alle1_tlbmask(env)); + raw_write128(env, ri, vallo, valhi); +} + static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_ALIAS, @@ -3339,26 +3374,35 @@ static void define_ttbr_registers(ARMCPU *cpu) { .name = "TTBR0_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, - .fgt = FGT_TTBR0_EL1, + .access128fn = access_tvm_trvm_d128, + .fgt = FGT_TTBR0_EL1, .type = ARM_CP_128BIT, .nv2_redirect_offset = 0x200 | NV2_REDIR_NV1, .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 0, 0), .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 0, 0), .writefn = vmsa_ttbr_write, .raw_writefn = raw_write, - .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[1]) }, + .write128fn = vmsa_ttbr_write128, .raw_write128fn = raw_write128, + .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[1]), + .fieldoffsethi = offsetof(CPUARMState, cp15.ttbr0_el_hi[1]) }, { .name = "TTBR1_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, - .fgt = FGT_TTBR1_EL1, + .access128fn = access_tvm_trvm_d128, + .fgt = FGT_TTBR1_EL1, .type = ARM_CP_128BIT, .nv2_redirect_offset = 0x210 | NV2_REDIR_NV1, .vhe_redir_to_el2 = ENCODE_AA64_CP_REG(3, 4, 2, 0, 1), .vhe_redir_to_el01 = ENCODE_AA64_CP_REG(3, 5, 2, 0, 1), .writefn = vmsa_ttbr_write, .raw_writefn = raw_write, - .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[1]) }, + .write128fn = vmsa_ttbr_write128, .raw_write128fn = raw_write128, + .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[1]), + .fieldoffsethi = offsetof(CPUARMState, cp15.ttbr1_el_hi[1]) }, { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, - .access = PL2_RW, .resetvalue = 0, + .access = PL2_RW, .access128fn = access_d128, .type = ARM_CP_128BIT, .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, - .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, + .write128fn = vmsa_tcr_ttbr_el2_write128, + .raw_write128fn = raw_write128, + .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]), + .fieldoffsethi = offsetof(CPUARMState, cp15.ttbr0_el_hi[2]) }, { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0, .access = PL3_RW, .resetvalue = 0, @@ -4548,9 +4592,13 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .writefn = vttbr_write, .raw_writefn = raw_write }, { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, - .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, + .type = ARM_CP_128BIT, + .access = PL2_RW, .access128fn = access_d128, + .writefn = vttbr_write, .raw_writefn = raw_write, + .write128fn = vttbr_write128, .raw_write128fn = raw_write128, .nv2_redirect_offset = 0x20, - .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, + .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), + .fieldoffsethi = offsetof(CPUARMState, cp15.vttbr_el2_hi) }, { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write, @@ -6196,9 +6244,12 @@ static const ARMCPRegInfo contextidr_el2 = { static const ARMCPRegInfo vhe_reginfo[] = { { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, - .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, - .raw_writefn = raw_write, - .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, + .type = ARM_CP_128BIT, + .access = PL2_RW, .access128fn = access_d128, + .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, + .write128fn = vmsa_tcr_ttbr_el2_write128, .raw_write128fn = raw_write128, + .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]), + .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el_hi[2]) }, #ifndef CONFIG_USER_ONLY { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 3, .opc2 = 2, -- 2.43.0