From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, philmd@linaro.org,
alistair.francis@wdc.com, palmer@dabbelt.com
Subject: [PATCH v3 06/34] target/riscv: Combine mhpmevent and mhpmeventh
Date: Tue, 14 Oct 2025 22:34:43 +0200 [thread overview]
Message-ID: <20251014203512.26282-7-anjo@rev.ng> (raw)
In-Reply-To: <20251014203512.26282-1-anjo@rev.ng>
According to version 20250508 of the privileged specification,
mhpmeventn is 64 bits in size and mhpmeventnh is only ever used
when XLEN == 32 and accesses the top 32 bits of the 64-bit
mhpmeventn registers. Combine the two arrays of target_ulong
mhpmeventh[] and mhpmevent[] to a single array of uint64_t.
This also allows for some minor code simplification where branches
handling either mhpmeventh[] or mhpmevent[] could be combined.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 10 +++----
target/riscv/csr.c | 67 +++++++++++++++---------------------------
target/riscv/machine.c | 3 +-
target/riscv/pmu.c | 53 ++++++++-------------------------
4 files changed, 42 insertions(+), 91 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 25f996985b..674a800d2f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -427,11 +427,11 @@ struct CPUArchState {
/* PMU counter state */
PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS];
- /* PMU event selector configured values. First three are unused */
- target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS];
-
- /* PMU event selector configured values for RV32 */
- target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS];
+ /*
+ * PMU event selector configured values. First three are unused.
+ * For RV32 top 32 bits are accessed via the mhpmeventh CSR.
+ */
+ uint64_t mhpmevent_val[RV_MAX_MHPMEVENTS];
PMUFixedCtrState pmu_fixed_ctrs[2];
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 8be33d8f2c..55110b4b66 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1168,8 +1168,9 @@ static RISCVException read_mhpmevent(CPURISCVState *env, int csrno,
target_ulong *val)
{
int evt_index = csrno - CSR_MCOUNTINHIBIT;
+ bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
- *val = env->mhpmevent_val[evt_index];
+ *val = extract64(env->mhpmevent_val[evt_index], 0, rv32 ? 32 : 64);
return RISCV_EXCP_NONE;
}
@@ -1178,13 +1179,11 @@ static RISCVException write_mhpmevent(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
int evt_index = csrno - CSR_MCOUNTINHIBIT;
- uint64_t mhpmevt_val = val;
+ uint64_t mhpmevt_val;
uint64_t inh_avail_mask;
if (riscv_cpu_mxl(env) == MXL_RV32) {
- env->mhpmevent_val[evt_index] = val;
- mhpmevt_val = mhpmevt_val |
- ((uint64_t)env->mhpmeventh_val[evt_index] << 32);
+ mhpmevt_val = deposit64(env->mhpmevent_val[evt_index], 0, 32, val);
} else {
inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MHPMEVENT_BIT_MINH;
inh_avail_mask |= riscv_has_ext(env, RVU) ? MHPMEVENT_BIT_UINH : 0;
@@ -1194,9 +1193,9 @@ static RISCVException write_mhpmevent(CPURISCVState *env, int csrno,
inh_avail_mask |= (riscv_has_ext(env, RVH) &&
riscv_has_ext(env, RVS)) ? MHPMEVENT_BIT_VSINH : 0;
mhpmevt_val = val & inh_avail_mask;
- env->mhpmevent_val[evt_index] = mhpmevt_val;
}
+ env->mhpmevent_val[evt_index] = mhpmevt_val;
riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
return RISCV_EXCP_NONE;
@@ -1207,7 +1206,7 @@ static RISCVException read_mhpmeventh(CPURISCVState *env, int csrno,
{
int evt_index = csrno - CSR_MHPMEVENT3H + 3;
- *val = env->mhpmeventh_val[evt_index];
+ *val = extract64(env->mhpmevent_val[evt_index], 32, 32);
return RISCV_EXCP_NONE;
}
@@ -1216,8 +1215,6 @@ static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno,
target_ulong val, uintptr_t ra)
{
int evt_index = csrno - CSR_MHPMEVENT3H + 3;
- uint64_t mhpmevth_val;
- uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
target_ulong inh_avail_mask = (target_ulong)(~MHPMEVENTH_FILTER_MASK |
MHPMEVENTH_BIT_MINH);
@@ -1228,11 +1225,10 @@ static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno,
inh_avail_mask |= (riscv_has_ext(env, RVH) &&
riscv_has_ext(env, RVS)) ? MHPMEVENTH_BIT_VSINH : 0;
- mhpmevth_val = val & inh_avail_mask;
- mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);
- env->mhpmeventh_val[evt_index] = mhpmevth_val;
+ env->mhpmevent_val[evt_index] = deposit64(env->mhpmevent_val[evt_index],
+ 32, 32, val & inh_avail_mask);
- riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
+ riscv_pmu_update_event_map(env, env->mhpmevent_val[evt_index], evt_index);
return RISCV_EXCP_NONE;
}
@@ -1258,9 +1254,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
cfg_val = rv32 ? ((uint64_t)env->minstretcfgh << 32) :
env->minstretcfg;
} else {
- cfg_val = rv32 ?
- ((uint64_t)env->mhpmeventh_val[counter_idx] << 32) :
- env->mhpmevent_val[counter_idx];
+ cfg_val = env->mhpmevent_val[counter_idx];
cfg_val &= MHPMEVENT_FILTER_MASK;
}
@@ -1473,27 +1467,23 @@ static int rmw_cd_mhpmcounterh(CPURISCVState *env, int ctr_idx,
static int rmw_cd_mhpmevent(CPURISCVState *env, int evt_index,
target_ulong *val, target_ulong new_val,
- target_ulong wr_mask)
+ uint64_t wr_mask)
{
- uint64_t mhpmevt_val = new_val;
+ uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
if (wr_mask != 0 && wr_mask != -1) {
return -EINVAL;
}
if (!wr_mask && val) {
- *val = env->mhpmevent_val[evt_index];
+ *val = mhpmevt_val;
if (riscv_cpu_cfg(env)->ext_sscofpmf) {
*val &= ~MHPMEVENT_BIT_MINH;
}
} else if (wr_mask) {
wr_mask &= ~MHPMEVENT_BIT_MINH;
- mhpmevt_val = (new_val & wr_mask) |
- (env->mhpmevent_val[evt_index] & ~wr_mask);
- if (riscv_cpu_mxl(env) == MXL_RV32) {
- mhpmevt_val = mhpmevt_val |
- ((uint64_t)env->mhpmeventh_val[evt_index] << 32);
- }
+ /* wr_mask is 64-bit so upper 32 bits of mhpmevt_val are retained */
+ mhpmevt_val = (new_val & wr_mask) | (mhpmevt_val & ~wr_mask);
env->mhpmevent_val[evt_index] = mhpmevt_val;
riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
} else {
@@ -1507,24 +1497,23 @@ static int rmw_cd_mhpmeventh(CPURISCVState *env, int evt_index,
target_ulong *val, target_ulong new_val,
target_ulong wr_mask)
{
- uint64_t mhpmevth_val;
uint64_t mhpmevt_val = env->mhpmevent_val[evt_index];
+ uint32_t mhpmevth_val = extract64(mhpmevt_val, 32, 32);
if (wr_mask != 0 && wr_mask != -1) {
return -EINVAL;
}
if (!wr_mask && val) {
- *val = env->mhpmeventh_val[evt_index];
+ *val = mhpmevth_val;
if (riscv_cpu_cfg(env)->ext_sscofpmf) {
*val &= ~MHPMEVENTH_BIT_MINH;
}
} else if (wr_mask) {
wr_mask &= ~MHPMEVENTH_BIT_MINH;
- env->mhpmeventh_val[evt_index] =
- (new_val & wr_mask) | (env->mhpmeventh_val[evt_index] & ~wr_mask);
- mhpmevth_val = env->mhpmeventh_val[evt_index];
- mhpmevt_val = mhpmevt_val | (mhpmevth_val << 32);
+ mhpmevth_val = (new_val & wr_mask) | (mhpmevth_val & ~wr_mask);
+ mhpmevt_val = deposit64(mhpmevt_val, 32, 32, mhpmevth_val);
+ env->mhpmevent_val[evt_index] = mhpmevt_val;
riscv_pmu_update_event_map(env, mhpmevt_val, evt_index);
} else {
return -EINVAL;
@@ -1600,8 +1589,6 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno,
int mhpmevt_start = CSR_MHPMEVENT3 - CSR_MCOUNTINHIBIT;
int i;
*val = 0;
- target_ulong *mhpm_evt_val;
- uint64_t of_bit_mask;
/* Virtualize scountovf for counter delegation */
if (riscv_cpu_cfg(env)->ext_sscofpmf &&
@@ -1611,19 +1598,11 @@ static RISCVException read_scountovf(CPURISCVState *env, int csrno,
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
- if (riscv_cpu_mxl(env) == MXL_RV32) {
- mhpm_evt_val = env->mhpmeventh_val;
- of_bit_mask = MHPMEVENTH_BIT_OF;
- } else {
- mhpm_evt_val = env->mhpmevent_val;
- of_bit_mask = MHPMEVENT_BIT_OF;
- }
-
for (i = mhpmevt_start; i < RV_MAX_MHPMEVENTS; i++) {
if ((get_field(env->mcounteren, BIT(i))) &&
- (mhpm_evt_val[i] & of_bit_mask)) {
- *val |= BIT(i);
- }
+ (env->mhpmevent_val[i] & MHPMEVENT_BIT_OF)) {
+ *val |= BIT(i);
+ }
}
return RISCV_EXCP_NONE;
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index ab0bc32e1f..6146124229 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -477,8 +477,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT32(env.mcountinhibit, RISCVCPU),
VMSTATE_STRUCT_ARRAY(env.pmu_ctrs, RISCVCPU, RV_MAX_MHPMCOUNTERS, 0,
vmstate_pmu_ctr_state, PMUCTRState),
- VMSTATE_UINTTL_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
- VMSTATE_UINTTL_ARRAY(env.mhpmeventh_val, RISCVCPU, RV_MAX_MHPMEVENTS),
+ VMSTATE_UINT64_ARRAY(env.mhpmevent_val, RISCVCPU, RV_MAX_MHPMEVENTS),
VMSTATE_UINT64(env.sscratch, RISCVCPU),
VMSTATE_UINT64(env.mscratch, RISCVCPU),
VMSTATE_UINT64(env.stimecmp, RISCVCPU),
diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c
index a68809eef3..273822e921 100644
--- a/target/riscv/pmu.c
+++ b/target/riscv/pmu.c
@@ -110,15 +110,15 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
/* Privilege mode filtering */
if ((env->priv == PRV_M &&
- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_MINH)) ||
+ (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_MINH)) ||
(env->priv == PRV_S && virt_on &&
- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VSINH)) ||
+ (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VSINH)) ||
(env->priv == PRV_U && virt_on &&
- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_VUINH)) ||
+ (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_VUINH)) ||
(env->priv == PRV_S && !virt_on &&
- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_SINH)) ||
+ (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_SINH)) ||
(env->priv == PRV_U && !virt_on &&
- (env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_UINH))) {
+ (env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_UINH))) {
return 0;
}
@@ -128,8 +128,8 @@ static int riscv_pmu_incr_ctr_rv32(RISCVCPU *cpu, uint32_t ctr_idx)
counter->mhpmcounter_val = 0;
counter->mhpmcounterh_val = 0;
/* Generate interrupt only if OF bit is clear */
- if (!(env->mhpmeventh_val[ctr_idx] & MHPMEVENTH_BIT_OF)) {
- env->mhpmeventh_val[ctr_idx] |= MHPMEVENTH_BIT_OF;
+ if (!(env->mhpmevent_val[ctr_idx] & MHPMEVENT_BIT_OF)) {
+ env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
riscv_cpu_update_mip(env, MIP_LCOFIP, BOOL_TO_MASK(1));
}
} else {
@@ -420,41 +420,14 @@ int riscv_pmu_update_event_map(CPURISCVState *env, uint64_t value,
return 0;
}
-static bool pmu_hpmevent_is_of_set(CPURISCVState *env, uint32_t ctr_idx)
-{
- target_ulong mhpmevent_val;
- uint64_t of_bit_mask;
-
- if (riscv_cpu_mxl(env) == MXL_RV32) {
- mhpmevent_val = env->mhpmeventh_val[ctr_idx];
- of_bit_mask = MHPMEVENTH_BIT_OF;
- } else {
- mhpmevent_val = env->mhpmevent_val[ctr_idx];
- of_bit_mask = MHPMEVENT_BIT_OF;
- }
-
- return get_field(mhpmevent_val, of_bit_mask);
-}
-
static bool pmu_hpmevent_set_of_if_clear(CPURISCVState *env, uint32_t ctr_idx)
{
- target_ulong *mhpmevent_val;
- uint64_t of_bit_mask;
-
- if (riscv_cpu_mxl(env) == MXL_RV32) {
- mhpmevent_val = &env->mhpmeventh_val[ctr_idx];
- of_bit_mask = MHPMEVENTH_BIT_OF;
- } else {
- mhpmevent_val = &env->mhpmevent_val[ctr_idx];
- of_bit_mask = MHPMEVENT_BIT_OF;
- }
-
- if (!get_field(*mhpmevent_val, of_bit_mask)) {
- *mhpmevent_val |= of_bit_mask;
+ if (!get_field(env->mhpmevent_val[ctr_idx], MHPMEVENT_BIT_OF)) {
+ env->mhpmevent_val[ctr_idx] |= MHPMEVENT_BIT_OF;
return true;
+ } else {
+ return false;
}
-
- return false;
}
static void pmu_timer_trigger_irq(RISCVCPU *cpu,
@@ -479,7 +452,7 @@ static void pmu_timer_trigger_irq(RISCVCPU *cpu,
}
/* Generate interrupt only if OF bit is clear */
- if (pmu_hpmevent_is_of_set(env, ctr_idx)) {
+ if (get_field(env->mhpmevent_val[ctr_idx], MHPMEVENT_BIT_OF)) {
return;
}
@@ -538,7 +511,7 @@ int riscv_pmu_setup_timer(CPURISCVState *env, uint64_t value, uint32_t ctr_idx)
/* No need to setup a timer if LCOFI is disabled when OF is set */
if (!riscv_pmu_counter_valid(cpu, ctr_idx) || !cpu->cfg.ext_sscofpmf ||
- pmu_hpmevent_is_of_set(env, ctr_idx)) {
+ get_field(env->mhpmevent_val[ctr_idx], MHPMEVENT_BIT_OF)) {
return -1;
}
--
2.51.0
next prev parent reply other threads:[~2025-10-14 20:37 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-14 20:34 [PATCH v3 00/34] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 01/34] target/riscv: Use 32 bits for misa extensions Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 02/34] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 03/34] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-16 3:56 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 04/34] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-15 18:14 ` Pierrick Bouvier
2025-10-16 3:22 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 05/34] target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read Anton Johansson via
2025-10-15 19:12 ` Pierrick Bouvier
2025-10-16 3:05 ` Alistair Francis
2025-10-14 20:34 ` Anton Johansson via [this message]
2025-10-14 20:34 ` [PATCH v3 07/34] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 08/34] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 09/34] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-16 4:09 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 10/34] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-15 19:13 ` Pierrick Bouvier
2025-10-16 4:32 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 11/34] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-14 20:34 ` [PATCH v3 12/34] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-16 4:33 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 13/34] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-16 4:34 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 14/34] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-16 4:35 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 15/34] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-16 4:50 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 16/34] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-16 23:45 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 17/34] target/riscv: Fix size of retxh Anton Johansson via
2025-10-16 5:11 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 18/34] target/riscv: Fix size of ssp Anton Johansson via
2025-10-16 5:35 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 19/34] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-15 20:53 ` Philippe Mathieu-Daudé
2025-10-16 5:35 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 20/34] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-15 20:52 ` Philippe Mathieu-Daudé
2025-10-16 23:14 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 21/34] target/riscv: Fix size of priv Anton Johansson via
2025-10-16 23:00 ` Alistair Francis
2025-10-14 20:34 ` [PATCH v3 22/34] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-16 23:15 ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 23/34] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 24/34] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 25/34] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-15 20:45 ` Philippe Mathieu-Daudé
2025-10-14 20:35 ` [PATCH v3 26/34] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-16 23:16 ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 27/34] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 28/34] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 29/34] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-15 20:51 ` Philippe Mathieu-Daudé
2025-10-23 10:46 ` Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 30/34] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 31/34] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-15 20:47 ` Philippe Mathieu-Daudé
2025-10-16 23:18 ` Alistair Francis
2025-10-14 20:35 ` [PATCH v3 32/34] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-15 20:49 ` Philippe Mathieu-Daudé
2025-10-14 20:35 ` [PATCH v3 33/34] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-14 20:35 ` [PATCH v3 34/34] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
2025-10-16 23:40 ` Alistair Francis
2025-10-15 20:58 ` [PATCH v3 00/34] single-binary: Make riscv cpu.h target independent Philippe Mathieu-Daudé
2025-10-16 3:30 ` Alistair Francis
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as well as URLs for NNTP newsgroup(s).