From: "Corvin Köhne" <corvin.koehne@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Kevin Wolf" <kwolf@redhat.com>,
"Yannick Voßen" <y.vossen@beckhoff.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
qemu-arm@nongnu.org, "Hanna Reitz" <hreitz@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-block@nongnu.org, "Corvin Köhne" <c.koehne@beckhoff.com>,
YannickV <Y.Vossen@beckhoff.com>
Subject: [PATCH v3 12/14] hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d
Date: Wed, 15 Oct 2025 11:17:27 +0200 [thread overview]
Message-ID: <20251015091729.33761-13-corvin.koehne@gmail.com> (raw)
In-Reply-To: <20251015091729.33761-1-corvin.koehne@gmail.com>
From: YannickV <Y.Vossen@beckhoff.com>
The is25lp016d has 4 Block Write Protect Bits. BP3 specifies
whether the upper or lower range should be protected. Therefore,
we add the HAS_SR_TB flag to the is25lp016d flags.
Signed-off-by: YannickV <Y.Vossen@beckhoff.com>
---
hw/block/m25p80.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
index a5336d92ff..1df223ee81 100644
--- a/hw/block/m25p80.c
+++ b/hw/block/m25p80.c
@@ -217,7 +217,8 @@ static const FlashPartInfo known_devices[] = {
/* ISSI */
{ INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) },
{ INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) },
- { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) },
+ { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32,
+ ER_4K | HAS_SR_TB) },
{ INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) },
{ INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) },
{ INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) },
--
2.47.3
next prev parent reply other threads:[~2025-10-15 9:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 9:17 [PATCH v3 00/14] hw/arm: add Beckhoff CX7200 board Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 01/14] hw/timer: Make frequency configurable Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 02/14] hw/timer: Make PERIPHCLK divider configurable Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 03/14] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 04/14] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 05/14] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 06/14] hw/dma/zynq-devcfg: Simulate dummy PL reset Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 07/14] hw/dma/zynq-devcfg: Indicate power-up status of PL Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 08/14] hw/dma/zynq-devcfg: Fix register memory Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 09/14] hw/misc: Add dummy ZYNQ DDR controller Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 10/14] hw/misc/zynq_slcr: Add logic for DCI configuration Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 11/14] hw/misc: Add Beckhoff CCAT device Corvin Köhne
2025-10-15 9:17 ` Corvin Köhne [this message]
2025-10-15 9:17 ` [PATCH v3 13/14] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 14/14] docs/system/arm: Add support " Corvin Köhne
2025-10-23 12:25 ` [PATCH v3 00/14] hw/arm: add Beckhoff CX7200 board Peter Maydell
2025-10-23 12:26 ` Peter Maydell
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