From: "Corvin Köhne" <corvin.koehne@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Kevin Wolf" <kwolf@redhat.com>,
"Yannick Voßen" <y.vossen@beckhoff.com>,
"Alistair Francis" <alistair@alistair23.me>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"Paolo Bonzini" <pbonzini@redhat.com>,
qemu-arm@nongnu.org, "Hanna Reitz" <hreitz@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
qemu-block@nongnu.org, "Corvin Köhne" <c.koehne@beckhoff.com>,
YannickV <Y.Vossen@beckhoff.com>,
"Edgar E. Iglesias" <edgar.iglesias@amd.com>
Subject: [PATCH v3 04/14] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization
Date: Wed, 15 Oct 2025 11:17:19 +0200 [thread overview]
Message-ID: <20251015091729.33761-5-corvin.koehne@gmail.com> (raw)
In-Reply-To: <20251015091729.33761-1-corvin.koehne@gmail.com>
From: YannickV <Y.Vossen@beckhoff.com>
During the emulation startup, all registers are reset, which triggers the
`r_unlock_post_write` function with a value of 0. This led to an
unintended memory access disable, making the devcfg unusable.
During startup, the memory space no longer gets locked.
Signed-off-by: YannickV <Y.Vossen@beckhoff.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
hw/dma/xlnx-zynq-devcfg.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
index f11d0e1b1c..72d73e93c7 100644
--- a/hw/dma/xlnx-zynq-devcfg.c
+++ b/hw/dma/xlnx-zynq-devcfg.c
@@ -221,7 +221,9 @@ static void r_unlock_post_write(RegisterInfo *reg, uint64_t val)
{
XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
const char *device_prefix = object_get_typename(OBJECT(s));
-
+ if (device_is_in_reset(DEVICE(s))) {
+ return;
+ }
if (val == R_UNLOCK_MAGIC) {
DB_PRINT("successful unlock\n");
s->regs[R_CTRL] |= R_CTRL_PCAP_PR_MASK;
--
2.47.3
next prev parent reply other threads:[~2025-10-15 9:22 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 9:17 [PATCH v3 00/14] hw/arm: add Beckhoff CX7200 board Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 01/14] hw/timer: Make frequency configurable Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 02/14] hw/timer: Make PERIPHCLK divider configurable Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 03/14] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff Corvin Köhne
2025-10-15 9:17 ` Corvin Köhne [this message]
2025-10-15 9:17 ` [PATCH v3 05/14] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 06/14] hw/dma/zynq-devcfg: Simulate dummy PL reset Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 07/14] hw/dma/zynq-devcfg: Indicate power-up status of PL Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 08/14] hw/dma/zynq-devcfg: Fix register memory Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 09/14] hw/misc: Add dummy ZYNQ DDR controller Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 10/14] hw/misc/zynq_slcr: Add logic for DCI configuration Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 11/14] hw/misc: Add Beckhoff CCAT device Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 12/14] hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 13/14] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Corvin Köhne
2025-10-15 9:17 ` [PATCH v3 14/14] docs/system/arm: Add support " Corvin Köhne
2025-10-23 12:25 ` [PATCH v3 00/14] hw/arm: add Beckhoff CX7200 board Peter Maydell
2025-10-23 12:26 ` Peter Maydell
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