From: Zhenzhong Duan <zhenzhong.duan@intel.com>
To: qemu-devel@nongnu.org
Cc: mst@redhat.com, jasowang@redhat.com, peterx@redhat.com,
yi.l.liu@intel.com, clement.mathieu--drif@eviden.com,
Zhenzhong Duan <zhenzhong.duan@intel.com>
Subject: [PATCH 2/3] intel_iommu: Reset pasid cache when system level reset
Date: Wed, 15 Oct 2025 06:20:01 -0400 [thread overview]
Message-ID: <20251015102003.279239-3-zhenzhong.duan@intel.com> (raw)
In-Reply-To: <20251015102003.279239-1-zhenzhong.duan@intel.com>
Reset pasid cache when system level reset, for PASID_0, its vtd_as is
allocated by PCI system and never removed, just mark pasid cache invalid.
As we already have vtd_pasid_cache_sync_locked() to handle pasid cache
invalidation, reuse it to do pasid cache invalidation at system reset
level.
Currently only IOMMUFD backed VFIO device caches pasid entry, so we don't
need to care about emulated device.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
---
hw/i386/intel_iommu_internal.h | 1 +
hw/i386/intel_iommu.c | 18 ++++++++++++++++--
hw/i386/trace-events | 1 +
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 80193ff28b..f6f2b7b8d5 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -618,6 +618,7 @@ typedef struct VTDPASIDCacheInfo {
uint8_t type;
uint16_t did;
uint32_t pasid;
+ bool reset;
} VTDPASIDCacheInfo;
/* PASID Table Related Definitions */
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 66f45f89cb..d656e9c256 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -86,6 +86,18 @@ struct vtd_iotlb_key {
static void vtd_address_space_refresh_all(IntelIOMMUState *s);
static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n);
+static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value,
+ gpointer user_data);
+
+static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s)
+{
+ VTDPASIDCacheInfo pc_info = { .reset = true };
+
+ trace_vtd_pasid_cache_reset();
+ g_hash_table_foreach(s->vtd_address_spaces,
+ vtd_pasid_cache_sync_locked, &pc_info);
+}
+
static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
uint64_t wmask, uint64_t w1cmask)
@@ -381,6 +393,7 @@ static void vtd_reset_caches(IntelIOMMUState *s)
vtd_iommu_lock(s);
vtd_reset_iotlb_locked(s);
vtd_reset_context_cache_locked(s);
+ vtd_pasid_cache_reset_locked(s);
vtd_iommu_unlock(s);
}
@@ -3083,11 +3096,12 @@ static void vtd_pasid_cache_sync_locked(gpointer key, gpointer value,
VTDPASIDEntry pe;
uint16_t did;
- if (vtd_dev_get_pe_from_pasid(vtd_as, &pe)) {
+ if (vtd_dev_get_pe_from_pasid(vtd_as, &pe) || pc_info->reset) {
/*
* No valid pasid entry in guest memory. e.g. pasid entry was modified
* to be either all-zero or non-present. Either case means existing
- * pasid cache should be invalidated.
+ * pasid cache should be invalidated. This also applies to system level
+ * reset where the whole guest memory is treated as zeroed.
*/
pc_entry->valid = false;
return;
diff --git a/hw/i386/trace-events b/hw/i386/trace-events
index 298addb24d..b704f4f90c 100644
--- a/hw/i386/trace-events
+++ b/hw/i386/trace-events
@@ -24,6 +24,7 @@ vtd_inv_qi_head(uint16_t head) "read head %d"
vtd_inv_qi_tail(uint16_t head) "write tail %d"
vtd_inv_qi_fetch(void) ""
vtd_context_cache_reset(void) ""
+vtd_pasid_cache_reset(void) ""
vtd_inv_desc_pasid_cache_gsi(void) ""
vtd_inv_desc_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation domain 0x%"PRIx16
vtd_inv_desc_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC invalidation domain 0x%"PRIx16" pasid 0x%"PRIx32
--
2.47.1
next prev parent reply other threads:[~2025-10-15 10:21 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 10:19 [PATCH 0/3] Fix DMA failure when there is domain switch in Zhenzhong Duan
2025-10-15 10:20 ` [PATCH 1/3] intel_iommu: Handle PASID cache invalidation Zhenzhong Duan
2025-10-15 12:38 ` Yi Liu
2025-10-16 2:45 ` Duan, Zhenzhong
2025-10-15 10:20 ` Zhenzhong Duan [this message]
2025-10-15 10:20 ` [PATCH 3/3] intel_iommu: Fix DMA failure when guest switches IOMMU domain Zhenzhong Duan
2025-10-15 12:42 ` Yi Liu
2025-10-16 3:14 ` Duan, Zhenzhong
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