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([71.212.157.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-29099a7d1bbsm6247085ad.65.2025.10.15.14.38.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Oct 2025 14:38:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, alex.bennee@linaro.org, Thomas Huth Subject: [PATCH v2 4/9] tcg/mips: Remove support for O32 and N32 ABIs Date: Wed, 15 Oct 2025 14:38:38 -0700 Message-ID: <20251015213843.14277-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251015213843.14277-1-richard.henderson@linaro.org> References: <20251015213843.14277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Philippe Mathieu-Daudé See previous commit for rationale. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Signed-off-by: Richard Henderson Message-ID: <20251009195210.33161-5-philmd@linaro.org> --- tcg/mips/tcg-target-reg-bits.h | 8 ++---- common-user/host/mips/safe-syscall.inc.S | 35 ------------------------ tcg/mips/tcg-target.c.inc | 14 ++-------- 3 files changed, 6 insertions(+), 51 deletions(-) diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h index 56fe0a725e..ee346a3f25 100644 --- a/tcg/mips/tcg-target-reg-bits.h +++ b/tcg/mips/tcg-target-reg-bits.h @@ -7,12 +7,10 @@ #ifndef TCG_TARGET_REG_BITS_H #define TCG_TARGET_REG_BITS_H -#if _MIPS_SIM == _ABIO32 -# define TCG_TARGET_REG_BITS 32 -#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 -# define TCG_TARGET_REG_BITS 64 -#else +#if !defined(_MIPS_SIM) || _MIPS_SIM != _ABI64 # error "Unknown ABI" #endif +#define TCG_TARGET_REG_BITS 64 + #endif diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S index 6a44614970..3b196cc634 100644 --- a/common-user/host/mips/safe-syscall.inc.S +++ b/common-user/host/mips/safe-syscall.inc.S @@ -30,15 +30,9 @@ * arguments being syscall arguments (also 'long'). */ -#if _MIPS_SIM == _ABIO32 -/* 8 * 4 = 32 for outgoing parameters; 1 * 4 for s0 save; 1 * 4 for align. */ -#define FRAME 40 -#define OFS_S0 32 -#else /* 1 * 8 for s0 save; 1 * 8 for align. */ #define FRAME 16 #define OFS_S0 0 -#endif NESTED(safe_syscall_base, FRAME, ra) @@ -47,34 +41,6 @@ NESTED(safe_syscall_base, FRAME, ra) .cfi_adjust_cfa_offset FRAME REG_S s0, OFS_S0(sp) .cfi_rel_offset s0, OFS_S0 -#if _MIPS_SIM == _ABIO32 - /* - * The syscall calling convention is nearly the same as C: - * we enter with a0 == &signal_pending - * a1 == syscall number - * a2, a3, stack == syscall arguments - * and return the result in a0 - * and the syscall instruction needs - * v0 == syscall number - * a0 ... a3, stack == syscall arguments - * and returns the result in v0 - * Shuffle everything around appropriately. - */ - move s0, a0 /* signal_pending pointer */ - move v0, a1 /* syscall number */ - move a0, a2 /* syscall arguments */ - move a1, a3 - lw a2, FRAME+16(sp) - lw a3, FRAME+20(sp) - lw t4, FRAME+24(sp) - lw t5, FRAME+28(sp) - lw t6, FRAME+32(sp) - lw t7, FRAME+40(sp) - sw t4, 16(sp) - sw t5, 20(sp) - sw t6, 24(sp) - sw t7, 28(sp) -#else /* * The syscall calling convention is nearly the same as C: * we enter with a0 == &signal_pending @@ -95,7 +61,6 @@ NESTED(safe_syscall_base, FRAME, ra) move a3, a5 move a4, a6 move a5, a7 -#endif /* * This next sequence of code works in conjunction with the diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 400eafbab4..2ca5aaf3a6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -26,16 +26,10 @@ /* used for function call generation */ #define TCG_TARGET_STACK_ALIGN 16 -#if _MIPS_SIM == _ABIO32 -# define TCG_TARGET_CALL_STACK_OFFSET 16 -# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF -#else -# define TCG_TARGET_CALL_STACK_OFFSET 0 -# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL -# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL -#endif +#define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #if TCG_TARGET_REG_BITS == 32 @@ -135,12 +129,10 @@ static const TCGReg tcg_target_call_iarg_regs[] = { TCG_REG_A1, TCG_REG_A2, TCG_REG_A3, -#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 TCG_REG_T0, TCG_REG_T1, TCG_REG_T2, TCG_REG_T3, -#endif }; static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) -- 2.43.0