From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 31/75] target/openrisc: Use vaddr type for $pc jumps
Date: Thu, 16 Oct 2025 14:14:47 +0200 [thread overview]
Message-ID: <20251016121532.14042-32-philmd@linaro.org> (raw)
In-Reply-To: <20251016121532.14042-1-philmd@linaro.org>
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010070702.51484-6-philmd@linaro.org>
---
target/openrisc/translate.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 5ab3bc7021d..9f61f917b3b 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -51,7 +51,7 @@ typedef struct DisasContext {
uint32_t avr;
/* If not -1, jmp_pc contains this value and so is a direct jump. */
- target_ulong jmp_pc_imm;
+ vaddr jmp_pc_imm;
/* The temporary corresponding to register 0 for this compilation. */
TCGv R0;
@@ -580,7 +580,7 @@ static bool trans_l_muldu(DisasContext *dc, arg_ab *a)
static bool trans_l_j(DisasContext *dc, arg_l_j *a)
{
- target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
+ vaddr tmp_pc = dc->base.pc_next + a->n * 4;
tcg_gen_movi_tl(jmp_pc, tmp_pc);
dc->jmp_pc_imm = tmp_pc;
@@ -590,8 +590,8 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a)
static bool trans_l_jal(DisasContext *dc, arg_l_jal *a)
{
- target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
- target_ulong ret_pc = dc->base.pc_next + 8;
+ vaddr tmp_pc = dc->base.pc_next + a->n * 4;
+ vaddr ret_pc = dc->base.pc_next + 8;
tcg_gen_movi_tl(cpu_regs[9], ret_pc);
/* Optimize jal being used to load the PC for PIC. */
@@ -605,7 +605,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a)
static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
{
- target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
+ vaddr tmp_pc = dc->base.pc_next + a->n * 4;
TCGv t_next = tcg_constant_tl(dc->base.pc_next + 8);
TCGv t_true = tcg_constant_tl(tmp_pc);
@@ -1586,7 +1586,7 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- target_ulong jmp_dest;
+ vaddr jmp_dest;
/* If we have already exited the TB, nothing following has effect. */
if (dc->base.is_jmp == DISAS_NORETURN) {
--
2.51.0
next prev parent reply other threads:[~2025-10-16 12:19 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 12:14 [PULL 00/75] Misc single binary patches for 2025-10-16 Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 01/75] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 02/75] target/alpha: Access CPUState::cpu_index via helper Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 03/75] target/alpha: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 04/75] target/hppa: Use hwaddr type for HPPATLBEntry::pa Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 05/75] target/hppa: Have hppa_form_gva*() return vaddr type Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 06/75] target/hppa: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 07/75] target/hppa: Conceal MO_TE within do_load() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 08/75] target/hppa: Conceal MO_TE within do_load_32/64() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 09/75] target/hppa: Conceal MO_TE within do_store() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 10/75] target/hppa: Conceal MO_TE within do_store_32/64() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 11/75] target/hppa: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 12/75] target/hppa: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 13/75] target/hppa: correct size bit parity for fmpyadd Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 14/75] target/loongarch: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 15/75] target/loongarch: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 16/75] target/loongarch: Remove target_ulong use in gdb_write_register handler Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 17/75] target/loongarch: Do not use target_ulong type for LDDIR level Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 18/75] target/m68k: Remove unused @cpu_exception_index TCGv Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 19/75] target/m68k: Remove pointless @cpu_halted TCGv Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 20/75] target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 21/75] target/microblaze: Remove target_ulong uses in get_phys_page_attrs_debug Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 22/75] target/microblaze: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 23/75] target/microblaze: Remove target_ulong use in helper_stackprot() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 24/75] target/microblaze: Have compute_ldst_addr_type[ab] return TCGv_i32 Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 25/75] target/microblaze: Have do_load/store() take a TCGv_i32 address argument Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 26/75] target/microblaze: Convert CPUMBState::res_addr field to uint32_t type Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 27/75] target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 28/75] target/openrisc: Do not use target_ulong for @mr in MTSPR helper Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 29/75] target/openrisc: Remove unused cpu_openrisc_map_address_*() handlers Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 30/75] target/openrisc: Remove target_ulong use in raise_mmu_exception() Philippe Mathieu-Daudé
2025-10-16 12:14 ` Philippe Mathieu-Daudé [this message]
2025-10-16 12:14 ` [PULL 32/75] target/openrisc: Remove 'TARGET_LONG_BITS != 32' dead code Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 33/75] target/openrisc: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 34/75] target/openrisc: Conceal MO_TE within do_load() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 35/75] target/openrisc: Conceal MO_TE within do_store() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 36/75] target/openrisc: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 37/75] target/openrisc: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 38/75] target/openrisc: Inline tcg_gen_trunc_i64_tl() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 39/75] target/openrisc: Replace target_ulong -> uint32_t Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 40/75] target/riscv: Use 32 bits for misa extensions Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 41/75] target/riscv: Replace HOST_BIG_ENDIAN #ifdef with if() check Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 42/75] target/rx: Replace target_ulong -> vaddr for translator API uses Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 43/75] target/rx: Use MemOp type in gen_ld[u]() and gen_st() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 44/75] target/rx: Propagate DisasContext to generated helpers Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 45/75] target/rx: Propagate DisasContext to push() / pop() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 46/75] target/rx: Propagate DisasContext to gen_ld[u]() and gen_st() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 47/75] target/rx: Factor mo_endian() helper out Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 48/75] target/rx: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 49/75] target/rx: Expand TCG register definitions for 32-bit target Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 50/75] target/rx: Un-inline various helpers Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 51/75] target/s390x: Replace HOST_BIG_ENDIAN #ifdef with if() check Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 52/75] target/sh4: Convert CPUSH4State::sr register to uint32_t type Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 53/75] target/sh4: Remove target_ulong use in cpu_sh4_is_cached() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 54/75] target/sh4: Use hwaddr type for hardware addresses Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 55/75] target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 56/75] target/sh4: Use vaddr type for TLB virtual addresses Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 57/75] target/sh4: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 58/75] target/sparc: Reduce inclusions of 'exec/cpu-common.h' Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 59/75] target/tricore: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 60/75] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 61/75] target/tricore: Remove target_ulong use in translate_insn() handler Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 62/75] target/tricore: Remove target_ulong use in gen_addi_d() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 63/75] target/tricore: Remove unnecessary cast to target_ulong Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 64/75] target/tricore: Replace target_ulong -> uint32_t in op_helper.c Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 65/75] target/tricore: Declare registers as TCGv_i32 Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 66/75] target/tricore: Inline tcg_gen_ld32u_tl() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 67/75] target/tricore: Expand TCG helpers for 32-bit target Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 68/75] target/tricore: Pass DisasContext as first argument Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 69/75] target/tricore: Un-inline various helpers Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 70/75] target/tricore: Expand TCGv type for 32-bit target Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 71/75] target/xtensa: Replace legacy cpu_physical_memory_[un]map() calls Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 72/75] target/xtensa: Remove target_ulong use in xtensa_tr_translate_insn() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 73/75] target/xtensa: Remove target_ulong use in xtensa_get_tb_cpu_state() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 74/75] linux-user/microblaze: Fix little-endianness binary Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 75/75] mailmap: Unify Clément Mathieu--Drif emails Philippe Mathieu-Daudé
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