From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 33/75] target/openrisc: Explode MO_TExx -> MO_TE | MO_xx
Date: Thu, 16 Oct 2025 14:14:49 +0200 [thread overview]
Message-ID: <20251016121532.14042-34-philmd@linaro.org> (raw)
In-Reply-To: <20251016121532.14042-1-philmd@linaro.org>
Extract the implicit MO_TE definition in order to replace
it in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/openrisc); \
done
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251010070702.51484-8-philmd@linaro.org>
---
target/openrisc/translate.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 29e6b51a930..52d51313f77 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -622,7 +622,7 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a)
check_r0_write(dc, a->d);
ea = tcg_temp_new();
tcg_gen_addi_tl(ea, cpu_R(dc, a->a), a->i);
- tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TEUL);
+ tcg_gen_qemu_ld_tl(cpu_R(dc, a->d), ea, dc->mem_idx, MO_TE | MO_UL);
tcg_gen_mov_tl(cpu_lock_addr, ea);
tcg_gen_mov_tl(cpu_lock_value, cpu_R(dc, a->d));
return true;
@@ -640,13 +640,13 @@ static void do_load(DisasContext *dc, arg_load *a, MemOp mop)
static bool trans_l_lwz(DisasContext *dc, arg_load *a)
{
- do_load(dc, a, MO_TEUL);
+ do_load(dc, a, MO_TE | MO_UL);
return true;
}
static bool trans_l_lws(DisasContext *dc, arg_load *a)
{
- do_load(dc, a, MO_TESL);
+ do_load(dc, a, MO_TE | MO_SL);
return true;
}
@@ -664,13 +664,13 @@ static bool trans_l_lbs(DisasContext *dc, arg_load *a)
static bool trans_l_lhz(DisasContext *dc, arg_load *a)
{
- do_load(dc, a, MO_TEUW);
+ do_load(dc, a, MO_TE | MO_UW);
return true;
}
static bool trans_l_lhs(DisasContext *dc, arg_load *a)
{
- do_load(dc, a, MO_TESW);
+ do_load(dc, a, MO_TE | MO_SW);
return true;
}
@@ -688,7 +688,7 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a)
val = tcg_temp_new();
tcg_gen_atomic_cmpxchg_tl(val, cpu_lock_addr, cpu_lock_value,
- cpu_R(dc, a->b), dc->mem_idx, MO_TEUL);
+ cpu_R(dc, a->b), dc->mem_idx, MO_TE | MO_UL);
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, val, cpu_lock_value);
tcg_gen_br(lab_done);
@@ -710,7 +710,7 @@ static void do_store(DisasContext *dc, arg_store *a, MemOp mop)
static bool trans_l_sw(DisasContext *dc, arg_store *a)
{
- do_store(dc, a, MO_TEUL);
+ do_store(dc, a, MO_TE | MO_UL);
return true;
}
@@ -722,7 +722,7 @@ static bool trans_l_sb(DisasContext *dc, arg_store *a)
static bool trans_l_sh(DisasContext *dc, arg_store *a)
{
- do_store(dc, a, MO_TEUW);
+ do_store(dc, a, MO_TE | MO_UW);
return true;
}
--
2.51.0
next prev parent reply other threads:[~2025-10-16 12:36 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 12:14 [PULL 00/75] Misc single binary patches for 2025-10-16 Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 01/75] accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 02/75] target/alpha: Access CPUState::cpu_index via helper Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 03/75] target/alpha: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 04/75] target/hppa: Use hwaddr type for HPPATLBEntry::pa Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 05/75] target/hppa: Have hppa_form_gva*() return vaddr type Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 06/75] target/hppa: Explode MO_TExx -> MO_TE | MO_xx Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 07/75] target/hppa: Conceal MO_TE within do_load() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 08/75] target/hppa: Conceal MO_TE within do_load_32/64() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 09/75] target/hppa: Conceal MO_TE within do_store() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 10/75] target/hppa: Conceal MO_TE within do_store_32/64() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 11/75] target/hppa: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 12/75] target/hppa: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 13/75] target/hppa: correct size bit parity for fmpyadd Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 14/75] target/loongarch: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 15/75] target/loongarch: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 16/75] target/loongarch: Remove target_ulong use in gdb_write_register handler Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 17/75] target/loongarch: Do not use target_ulong type for LDDIR level Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 18/75] target/m68k: Remove unused @cpu_exception_index TCGv Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 19/75] target/m68k: Remove pointless @cpu_halted TCGv Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 20/75] target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 21/75] target/microblaze: Remove target_ulong uses in get_phys_page_attrs_debug Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 22/75] target/microblaze: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 23/75] target/microblaze: Remove target_ulong use in helper_stackprot() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 24/75] target/microblaze: Have compute_ldst_addr_type[ab] return TCGv_i32 Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 25/75] target/microblaze: Have do_load/store() take a TCGv_i32 address argument Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 26/75] target/microblaze: Convert CPUMBState::res_addr field to uint32_t type Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 27/75] target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 28/75] target/openrisc: Do not use target_ulong for @mr in MTSPR helper Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 29/75] target/openrisc: Remove unused cpu_openrisc_map_address_*() handlers Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 30/75] target/openrisc: Remove target_ulong use in raise_mmu_exception() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 31/75] target/openrisc: Use vaddr type for $pc jumps Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 32/75] target/openrisc: Remove 'TARGET_LONG_BITS != 32' dead code Philippe Mathieu-Daudé
2025-10-16 12:14 ` Philippe Mathieu-Daudé [this message]
2025-10-16 12:14 ` [PULL 34/75] target/openrisc: Conceal MO_TE within do_load() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 35/75] target/openrisc: Conceal MO_TE within do_store() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 36/75] target/openrisc: Introduce mo_endian() helper Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 37/75] target/openrisc: Replace MO_TE -> MO_BE Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 38/75] target/openrisc: Inline tcg_gen_trunc_i64_tl() Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 39/75] target/openrisc: Replace target_ulong -> uint32_t Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 40/75] target/riscv: Use 32 bits for misa extensions Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 41/75] target/riscv: Replace HOST_BIG_ENDIAN #ifdef with if() check Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 42/75] target/rx: Replace target_ulong -> vaddr for translator API uses Philippe Mathieu-Daudé
2025-10-16 12:14 ` [PULL 43/75] target/rx: Use MemOp type in gen_ld[u]() and gen_st() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 44/75] target/rx: Propagate DisasContext to generated helpers Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 45/75] target/rx: Propagate DisasContext to push() / pop() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 46/75] target/rx: Propagate DisasContext to gen_ld[u]() and gen_st() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 47/75] target/rx: Factor mo_endian() helper out Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 48/75] target/rx: Replace MO_TE -> MO_LE Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 49/75] target/rx: Expand TCG register definitions for 32-bit target Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 50/75] target/rx: Un-inline various helpers Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 51/75] target/s390x: Replace HOST_BIG_ENDIAN #ifdef with if() check Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 52/75] target/sh4: Convert CPUSH4State::sr register to uint32_t type Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 53/75] target/sh4: Remove target_ulong use in cpu_sh4_is_cached() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 54/75] target/sh4: Use hwaddr type for hardware addresses Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 55/75] target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 56/75] target/sh4: Use vaddr type for TLB virtual addresses Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 57/75] target/sh4: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 58/75] target/sparc: Reduce inclusions of 'exec/cpu-common.h' Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 59/75] target/tricore: Remove target_ulong use in gen_goto_tb() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 60/75] target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 61/75] target/tricore: Remove target_ulong use in translate_insn() handler Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 62/75] target/tricore: Remove target_ulong use in gen_addi_d() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 63/75] target/tricore: Remove unnecessary cast to target_ulong Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 64/75] target/tricore: Replace target_ulong -> uint32_t in op_helper.c Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 65/75] target/tricore: Declare registers as TCGv_i32 Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 66/75] target/tricore: Inline tcg_gen_ld32u_tl() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 67/75] target/tricore: Expand TCG helpers for 32-bit target Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 68/75] target/tricore: Pass DisasContext as first argument Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 69/75] target/tricore: Un-inline various helpers Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 70/75] target/tricore: Expand TCGv type for 32-bit target Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 71/75] target/xtensa: Replace legacy cpu_physical_memory_[un]map() calls Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 72/75] target/xtensa: Remove target_ulong use in xtensa_tr_translate_insn() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 73/75] target/xtensa: Remove target_ulong use in xtensa_get_tb_cpu_state() Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 74/75] linux-user/microblaze: Fix little-endianness binary Philippe Mathieu-Daudé
2025-10-16 12:15 ` [PULL 75/75] mailmap: Unify Clément Mathieu--Drif emails Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20251016121532.14042-34-philmd@linaro.org \
--to=philmd@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).