From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-arm@nongnu.org, qemu-devel@nongnu.org
Cc: Vacha Bhavsar <vacha.bhavsar@oss.qualcomm.com>
Subject: [PATCH 0/2] target/arm: Support SME2 in gdbstub
Date: Thu, 16 Oct 2025 13:21:30 +0100 [thread overview]
Message-ID: <20251016122132.737016-1-peter.maydell@linaro.org> (raw)
This patchseries adds SME2 support to the gdbstub. This is
fairly straightforward as the only thing we need to do is
expose the new ZT0 register in the XML in the way that gdb
documents that we should.
Patch 2 is a simple "check reads and writes" test case along
the lines of our existing SME tests. I don't think there are
any specific gdb version requirements here because the XML
should be enough for gdb to know it's a 64 byte vector.
(I also did a little manual testing with a program that
reads and writes the ZT0 value in guest code to confirm that
gdb interactions do the right thing.)
thanks
-- PMM
Peter Maydell (2):
target/arm: Implement SME2 support in gdbstub
tests/tcg/aarch64: Add test case for SME2 gdbstub registers
target/arm/cpu.h | 1 +
target/arm/internals.h | 3 +
target/arm/gdbstub.c | 7 +++
target/arm/gdbstub64.c | 76 ++++++++++++++++++++++++++
tests/tcg/aarch64/Makefile.target | 9 ++-
tests/tcg/aarch64/gdbstub/test-sme2.py | 41 ++++++++++++++
6 files changed, 136 insertions(+), 1 deletion(-)
create mode 100644 tests/tcg/aarch64/gdbstub/test-sme2.py
--
2.43.0
next reply other threads:[~2025-10-16 12:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-16 12:21 Peter Maydell [this message]
2025-10-16 12:21 ` [PATCH 1/2] target/arm: Implement SME2 support in gdbstub Peter Maydell
2025-10-16 21:17 ` Richard Henderson
2025-10-17 14:14 ` Peter Maydell
2025-10-16 12:21 ` [PATCH 2/2] tests/tcg/aarch64: Add test case for SME2 gdbstub registers Peter Maydell
2025-10-16 21:19 ` Richard Henderson
2025-10-17 15:11 ` Peter Maydell
2025-10-16 21:10 ` [PATCH 0/2] target/arm: Support SME2 in gdbstub Richard Henderson
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