* [PULL v2 00/75] Misc single binary patches for 2025-10-16
@ 2025-10-16 15:11 Philippe Mathieu-Daudé
2025-10-16 15:11 ` [PULL v2 04/79] target/i386/monitor: Propagate CPU address space to 'info mem' handlers Philippe Mathieu-Daudé
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-16 15:11 UTC (permalink / raw)
To: qemu-devel
The following changes since commit 8109ebdb95c45d9062c7e6e7beae0ee571fca4f8:
Merge tag 'pull-loongarch-20251015' of https://github.com/bibo-mao/qemu into staging (2025-10-15 14:49:51 -0700)
are available in the Git repository at:
https://github.com/philmd/qemu.git tags/single-binary-20251016
for you to fetch changes up to 8dd133fa85bb49e2e61c489a566ab8460478dc24:
mailmap: Unify Clément Mathieu--Drif emails (2025-10-16 17:07:52 +0200)
v2: Remove legacy cpu_physical_memory_*() calls
----------------------------------------------------------------
Various patches related to single binary work:
- Remove some VMSTATE_UINTTL() uses
- Replace target_ulong by vaddr / hwaddr / uint[32,64]_t
- Expand TCGv to TCGv_i32 for 32-bit targets
- Remove some unnecessary checks on TARGET_LONG_BITS
- Replace few HOST_BIG_ENDIAN preprocessor #ifdef by compile-time if() check
- Expand MO_TE to either MO_BE or MO_LE
Also:
- Remove legacy cpu_physical_memory_*() calls
- Fix HPPA FMPYADD opcode
- Unify Clément Mathieu--Drif email addresses
----------------------------------------------------------------
Anton Johansson (1):
target/riscv: Use 32 bits for misa extensions
Gabriel Brookman (1):
target/hppa: correct size bit parity for fmpyadd
Philippe Mathieu-Daudé (77):
accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
target/alpha: Access CPUState::cpu_index via helper
target/alpha: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64()
target/i386/monitor: Propagate CPU address space to 'info mem'
handlers
target/i386/monitor: Replace legacy cpu_physical_memory_read() calls
target/hppa: Use hwaddr type for HPPATLBEntry::pa
target/hppa: Have hppa_form_gva*() return vaddr type
target/hppa: Explode MO_TExx -> MO_TE | MO_xx
target/hppa: Conceal MO_TE within do_load()
target/hppa: Conceal MO_TE within do_load_32/64()
target/hppa: Conceal MO_TE within do_store()
target/hppa: Conceal MO_TE within do_store_32/64()
target/hppa: Introduce mo_endian() helper
target/hppa: Replace MO_TE -> MO_BE
target/loongarch: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64()
target/loongarch: Remove target_ulong use in gen_goto_tb()
target/loongarch: Remove target_ulong use in gdb_write_register
handler
target/loongarch: Do not use target_ulong type for LDDIR level
target/m68k: Remove unused @cpu_exception_index TCGv
target/m68k: Remove pointless @cpu_halted TCGv
target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault()
target/microblaze: Remove target_ulong uses in
get_phys_page_attrs_debug
target/microblaze: Remove target_ulong use in gen_goto_tb()
target/microblaze: Remove target_ulong use in helper_stackprot()
target/microblaze: Have compute_ldst_addr_type[ab] return TCGv_i32
target/microblaze: Have do_load/store() take a TCGv_i32 address
argument
target/microblaze: Convert CPUMBState::res_addr field to uint32_t type
target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32()
target/openrisc: Do not use target_ulong for @mr in MTSPR helper
target/openrisc: Remove unused cpu_openrisc_map_address_*() handlers
target/openrisc: Remove target_ulong use in raise_mmu_exception()
target/openrisc: Use vaddr type for $pc jumps
target/openrisc: Remove 'TARGET_LONG_BITS != 32' dead code
target/openrisc: Explode MO_TExx -> MO_TE | MO_xx
target/openrisc: Conceal MO_TE within do_load()
target/openrisc: Conceal MO_TE within do_store()
target/openrisc: Introduce mo_endian() helper
target/openrisc: Replace MO_TE -> MO_BE
target/openrisc: Inline tcg_gen_trunc_i64_tl()
target/openrisc: Replace target_ulong -> uint32_t
target/riscv/kvm: Replace legacy cpu_physical_memory_read/write()
calls
target/riscv/monitor: Replace legacy cpu_physical_memory_read() call
target/riscv: Replace HOST_BIG_ENDIAN #ifdef with if() check
target/rx: Replace target_ulong -> vaddr for translator API uses
target/rx: Use MemOp type in gen_ld[u]() and gen_st()
target/rx: Propagate DisasContext to generated helpers
target/rx: Propagate DisasContext to push() / pop()
target/rx: Propagate DisasContext to gen_ld[u]() and gen_st()
target/rx: Factor mo_endian() helper out
target/rx: Replace MO_TE -> MO_LE
target/rx: Expand TCG register definitions for 32-bit target
target/rx: Un-inline various helpers
target/s390x: Replace HOST_BIG_ENDIAN #ifdef with if() check
target/sh4: Convert CPUSH4State::sr register to uint32_t type
target/sh4: Remove target_ulong use in cpu_sh4_is_cached()
target/sh4: Use hwaddr type for hardware addresses
target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug
target/sh4: Use vaddr type for TLB virtual addresses
target/sh4: Remove target_ulong use in gen_goto_tb()
target/sparc: Reduce inclusions of 'exec/cpu-common.h'
target/tricore: Remove target_ulong use in gen_goto_tb()
target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
target/tricore: Remove target_ulong use in translate_insn() handler
target/tricore: Remove target_ulong use in gen_addi_d()
target/tricore: Remove unnecessary cast to target_ulong
target/tricore: Replace target_ulong -> uint32_t in op_helper.c
target/tricore: Declare registers as TCGv_i32
target/tricore: Inline tcg_gen_ld32u_tl()
target/tricore: Expand TCG helpers for 32-bit target
target/tricore: Pass DisasContext as first argument
target/tricore: Un-inline various helpers
target/tricore: Expand TCGv type for 32-bit target
target/xtensa: Replace legacy cpu_physical_memory_[un]map() calls
target/xtensa: Remove target_ulong use in xtensa_tr_translate_insn()
target/xtensa: Remove target_ulong use in xtensa_get_tb_cpu_state()
linux-user/microblaze: Fix little-endianness binary
mailmap: Unify Clément Mathieu--Drif emails
target/alpha/helper.h | 1 +
target/hppa/cpu.h | 10 +-
target/loongarch/cpu-mmu.h | 2 +-
target/loongarch/tcg/helper.h | 2 +-
target/microblaze/cpu.h | 2 +-
target/microblaze/helper.h | 2 +-
target/microblaze/mmu.h | 2 +-
target/openrisc/cpu.h | 31 +-
target/openrisc/helper.h | 8 +-
target/riscv/cpu.h | 4 +-
target/sh4/cpu.h | 6 +-
target/sparc/cpu.h | 1 -
target/hppa/insns.decode | 8 +-
linux-user/microblaze/elfload.c | 3 +-
target/alpha/machine.c | 34 +-
target/alpha/sys_helper.c | 5 +
target/alpha/translate.c | 11 +-
target/arm/tcg/translate-a64.c | 8 +-
target/arm/tcg/translate.c | 8 +-
target/avr/translate.c | 7 +-
target/hexagon/translate.c | 8 +-
target/hppa/helper.c | 4 +-
target/hppa/mem_helper.c | 2 +-
target/hppa/translate.c | 24 +-
target/i386/monitor.c | 134 +-
target/loongarch/cpu_helper.c | 2 +-
target/loongarch/gdbstub.c | 2 +-
target/loongarch/machine.c | 4 +-
target/loongarch/tcg/tlb_helper.c | 4 +-
target/loongarch/tcg/translate.c | 6 +-
target/m68k/translate.c | 17 +-
target/microblaze/helper.c | 3 +-
target/microblaze/machine.c | 6 +-
target/microblaze/mmu.c | 4 +-
target/microblaze/op_helper.c | 4 +-
target/microblaze/translate.c | 83 +-
target/mips/tcg/translate.c | 7 +-
target/openrisc/fpu_helper.c | 8 +-
target/openrisc/machine.c | 20 +-
target/openrisc/mmu.c | 7 +-
target/openrisc/sys_helper.c | 7 +-
target/openrisc/translate.c | 463 +-
target/ppc/translate.c | 7 +-
target/riscv/kvm/kvm-cpu.c | 6 +-
target/riscv/monitor.c | 12 +-
target/riscv/translate.c | 9 +-
target/riscv/vector_helper.c | 32 +-
target/rx/translate.c | 462 +-
target/s390x/tcg/translate.c | 6 +-
target/sh4/helper.c | 34 +-
target/sh4/translate.c | 10 +-
target/sparc/helper.c | 1 +
target/sparc/int64_helper.c | 1 +
target/sparc/translate.c | 6 +-
target/tricore/cpu.c | 2 +-
target/tricore/helper.c | 4 +-
target/tricore/op_helper.c | 219 +-
target/tricore/translate.c | 3978 +++++++++--------
target/xtensa/cpu.c | 6 +-
target/xtensa/translate.c | 2 +-
target/xtensa/xtensa-semi.c | 11 +-
.../tcg/insn_trans/trans_privileged.c.inc | 2 +-
target/riscv/insn_trans/trans_rvv.c.inc | 16 +-
target/s390x/tcg/translate_vx.c.inc | 6 +-
.mailmap | 1 +
target/hppa/trace-events | 6 +-
66 files changed, 2925 insertions(+), 2888 deletions(-)
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PULL v2 04/79] target/i386/monitor: Propagate CPU address space to 'info mem' handlers
2025-10-16 15:11 [PULL v2 00/75] Misc single binary patches for 2025-10-16 Philippe Mathieu-Daudé
@ 2025-10-16 15:11 ` Philippe Mathieu-Daudé
2025-10-16 15:11 ` [PULL v2 05/79] target/i386/monitor: Replace legacy cpu_physical_memory_read() calls Philippe Mathieu-Daudé
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-16 15:11 UTC (permalink / raw)
To: qemu-devel
We want to replace the cpu_physical_memory_read() calls by
address_space_read() equivalents. Since the latter requires
an address space, and these commands are run in the context
of a vCPU, propagate its first address space. Next commit
will do the replacements.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20251002145742.75624-2-philmd@linaro.org>
---
target/i386/monitor.c | 38 +++++++++++++++++++++-----------------
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 3c9b6ca62f2..7e7854e6c1b 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -68,7 +68,7 @@ static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
pte & PG_RW_MASK ? 'W' : '-');
}
-static void tlb_info_32(Monitor *mon, CPUArchState *env)
+static void tlb_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
unsigned int l1, l2;
uint32_t pgd, pde, pte;
@@ -96,7 +96,7 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env)
}
}
-static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
+static void tlb_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
unsigned int l1, l2, l3;
uint64_t pdpe, pde, pte;
@@ -136,7 +136,7 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
}
#ifdef TARGET_X86_64
-static void tlb_info_la48(Monitor *mon, CPUArchState *env,
+static void tlb_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as,
uint64_t l0, uint64_t pml4_addr)
{
uint64_t l1, l2, l3, l4;
@@ -197,7 +197,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env,
}
}
-static void tlb_info_la57(Monitor *mon, CPUArchState *env)
+static void tlb_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
uint64_t l0;
uint64_t pml5e;
@@ -208,7 +208,7 @@ static void tlb_info_la57(Monitor *mon, CPUArchState *env)
cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
pml5e = le64_to_cpu(pml5e);
if (pml5e & PG_PRESENT_MASK) {
- tlb_info_la48(mon, env, l0, pml5e & 0x3fffffffff000ULL);
+ tlb_info_la48(mon, env, as, l0, pml5e & 0x3fffffffff000ULL);
}
}
}
@@ -217,6 +217,7 @@ static void tlb_info_la57(Monitor *mon, CPUArchState *env)
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
{
CPUArchState *env;
+ AddressSpace *as;
env = mon_get_cpu_env(mon);
if (!env) {
@@ -228,21 +229,22 @@ void hmp_info_tlb(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "PG disabled\n");
return;
}
+ as = cpu_get_address_space(env_cpu(env), X86ASIdx_MEM);
if (env->cr[4] & CR4_PAE_MASK) {
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
if (env->cr[4] & CR4_LA57_MASK) {
- tlb_info_la57(mon, env);
+ tlb_info_la57(mon, env, as);
} else {
- tlb_info_la48(mon, env, 0, env->cr[3] & 0x3fffffffff000ULL);
+ tlb_info_la48(mon, env, as, 0, env->cr[3] & 0x3fffffffff000ULL);
}
} else
#endif
{
- tlb_info_pae32(mon, env);
+ tlb_info_pae32(mon, env, as);
}
} else {
- tlb_info_32(mon, env);
+ tlb_info_32(mon, env, as);
}
}
@@ -271,7 +273,7 @@ static void mem_print(Monitor *mon, CPUArchState *env,
}
}
-static void mem_info_32(Monitor *mon, CPUArchState *env)
+static void mem_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
unsigned int l1, l2;
int prot, last_prot;
@@ -312,7 +314,7 @@ static void mem_info_32(Monitor *mon, CPUArchState *env)
mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 32, 0);
}
-static void mem_info_pae32(Monitor *mon, CPUArchState *env)
+static void mem_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
unsigned int l1, l2, l3;
int prot, last_prot;
@@ -369,7 +371,7 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env)
#ifdef TARGET_X86_64
-static void mem_info_la48(Monitor *mon, CPUArchState *env)
+static void mem_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
int prot, last_prot;
uint64_t l1, l2, l3, l4;
@@ -449,7 +451,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env)
mem_print(mon, env, &start, &last_prot, (hwaddr)1 << 48, 0);
}
-static void mem_info_la57(Monitor *mon, CPUArchState *env)
+static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
int prot, last_prot;
uint64_t l0, l1, l2, l3, l4;
@@ -545,6 +547,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env)
void hmp_info_mem(Monitor *mon, const QDict *qdict)
{
CPUArchState *env;
+ AddressSpace *as;
env = mon_get_cpu_env(mon);
if (!env) {
@@ -556,21 +559,22 @@ void hmp_info_mem(Monitor *mon, const QDict *qdict)
monitor_printf(mon, "PG disabled\n");
return;
}
+ as = cpu_get_address_space(env_cpu(env), X86ASIdx_MEM);
if (env->cr[4] & CR4_PAE_MASK) {
#ifdef TARGET_X86_64
if (env->hflags & HF_LMA_MASK) {
if (env->cr[4] & CR4_LA57_MASK) {
- mem_info_la57(mon, env);
+ mem_info_la57(mon, env, as);
} else {
- mem_info_la48(mon, env);
+ mem_info_la48(mon, env, as);
}
} else
#endif
{
- mem_info_pae32(mon, env);
+ mem_info_pae32(mon, env, as);
}
} else {
- mem_info_32(mon, env);
+ mem_info_32(mon, env, as);
}
}
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL v2 05/79] target/i386/monitor: Replace legacy cpu_physical_memory_read() calls
2025-10-16 15:11 [PULL v2 00/75] Misc single binary patches for 2025-10-16 Philippe Mathieu-Daudé
2025-10-16 15:11 ` [PULL v2 04/79] target/i386/monitor: Propagate CPU address space to 'info mem' handlers Philippe Mathieu-Daudé
@ 2025-10-16 15:11 ` Philippe Mathieu-Daudé
2025-10-16 15:11 ` [PULL v2 42/79] target/riscv/kvm: Replace legacy cpu_physical_memory_read/write() calls Philippe Mathieu-Daudé
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-16 15:11 UTC (permalink / raw)
To: qemu-devel
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Replace:
- cpu_physical_memory_read(len=4) -> address_space_ldl()
- cpu_physical_memory_read(len=8) -> address_space_ldq()
inlining the little endianness conversion via the '_le' suffix.
As with the previous implementation, ignore whether the memory
read succeeded or failed.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20251002145742.75624-3-philmd@linaro.org>
---
target/i386/monitor.c | 96 ++++++++++++++++++++-----------------------
1 file changed, 44 insertions(+), 52 deletions(-)
diff --git a/target/i386/monitor.c b/target/i386/monitor.c
index 7e7854e6c1b..d2bb873d494 100644
--- a/target/i386/monitor.c
+++ b/target/i386/monitor.c
@@ -30,6 +30,7 @@
#include "qobject/qdict.h"
#include "qapi/error.h"
#include "qapi/qapi-commands-misc.h"
+#include "system/memory.h"
/* Perform linear address sign extension */
static hwaddr addr_canonical(CPUArchState *env, hwaddr addr)
@@ -70,21 +71,21 @@ static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr,
static void tlb_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2;
uint32_t pgd, pde, pte;
pgd = env->cr[3] & ~0xfff;
for(l1 = 0; l1 < 1024; l1++) {
- cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
- pde = le32_to_cpu(pde);
+ pde = address_space_ldl_le(as, pgd + l1 * 4, attrs, NULL);
if (pde & PG_PRESENT_MASK) {
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
/* 4M pages */
print_pte(mon, env, (l1 << 22), pde, ~((1 << 21) - 1));
} else {
for(l2 = 0; l2 < 1024; l2++) {
- cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
- pte = le32_to_cpu(pte);
+ pte = address_space_ldl_le(as, (pde & ~0xfff) + l2 * 4,
+ attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l1 << 22) + (l2 << 12),
pte & ~PG_PSE_MASK,
@@ -98,19 +99,18 @@ static void tlb_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
static void tlb_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2, l3;
uint64_t pdpe, pde, pte;
uint64_t pdp_addr, pd_addr, pt_addr;
pdp_addr = env->cr[3] & ~0x1f;
for (l1 = 0; l1 < 4; l1++) {
- cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
- pdpe = le64_to_cpu(pdpe);
+ pdpe = address_space_ldq_le(as, pdp_addr + l1 * 8, attrs, NULL);
if (pdpe & PG_PRESENT_MASK) {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
- cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
- pde = le64_to_cpu(pde);
+ pde = address_space_ldq_le(as, pd_addr + l2 * 8, attrs, NULL);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
/* 2M pages with PAE, CR4.PSE is ignored */
@@ -119,8 +119,8 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
- cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
- pte = le64_to_cpu(pte);
+ pte = address_space_ldq_le(as, pt_addr + l3 * 8,
+ attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l1 << 30) + (l2 << 21)
+ (l3 << 12),
@@ -139,21 +139,20 @@ static void tlb_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
static void tlb_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as,
uint64_t l0, uint64_t pml4_addr)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
uint64_t l1, l2, l3, l4;
uint64_t pml4e, pdpe, pde, pte;
uint64_t pdp_addr, pd_addr, pt_addr;
for (l1 = 0; l1 < 512; l1++) {
- cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
- pml4e = le64_to_cpu(pml4e);
+ pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
if (!(pml4e & PG_PRESENT_MASK)) {
continue;
}
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
- cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
- pdpe = le64_to_cpu(pdpe);
+ pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
if (!(pdpe & PG_PRESENT_MASK)) {
continue;
}
@@ -167,8 +166,7 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as,
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
- cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
- pde = le64_to_cpu(pde);
+ pde = address_space_ldq_le(as, pd_addr + l3 * 8, attrs, NULL);
if (!(pde & PG_PRESENT_MASK)) {
continue;
}
@@ -182,10 +180,8 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as,
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
- cpu_physical_memory_read(pt_addr
- + l4 * 8,
- &pte, 8);
- pte = le64_to_cpu(pte);
+ pte = address_space_ldq_le(as, pt_addr + l4 * 8,
+ attrs, NULL);
if (pte & PG_PRESENT_MASK) {
print_pte(mon, env, (l0 << 48) + (l1 << 39) +
(l2 << 30) + (l3 << 21) + (l4 << 12),
@@ -199,14 +195,14 @@ static void tlb_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as,
static void tlb_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
uint64_t l0;
uint64_t pml5e;
uint64_t pml5_addr;
pml5_addr = env->cr[3] & 0x3fffffffff000ULL;
for (l0 = 0; l0 < 512; l0++) {
- cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
- pml5e = le64_to_cpu(pml5e);
+ pml5e = address_space_ldq_le(as, pml5_addr + l0 * 8, attrs, NULL);
if (pml5e & PG_PRESENT_MASK) {
tlb_info_la48(mon, env, as, l0, pml5e & 0x3fffffffff000ULL);
}
@@ -275,6 +271,7 @@ static void mem_print(Monitor *mon, CPUArchState *env,
static void mem_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2;
int prot, last_prot;
uint32_t pgd, pde, pte;
@@ -284,8 +281,7 @@ static void mem_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
last_prot = 0;
start = -1;
for(l1 = 0; l1 < 1024; l1++) {
- cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
- pde = le32_to_cpu(pde);
+ pde = address_space_ldl_le(as, pgd + l1 * 4, attrs, NULL);
end = l1 << 22;
if (pde & PG_PRESENT_MASK) {
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
@@ -293,8 +289,8 @@ static void mem_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
mem_print(mon, env, &start, &last_prot, end, prot);
} else {
for(l2 = 0; l2 < 1024; l2++) {
- cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
- pte = le32_to_cpu(pte);
+ pte = address_space_ldl_le(as, (pde & ~0xfff) + l2 * 4,
+ attrs, NULL);
end = (l1 << 22) + (l2 << 12);
if (pte & PG_PRESENT_MASK) {
prot = pte & pde &
@@ -316,6 +312,7 @@ static void mem_info_32(Monitor *mon, CPUArchState *env, AddressSpace *as)
static void mem_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
unsigned int l1, l2, l3;
int prot, last_prot;
uint64_t pdpe, pde, pte;
@@ -326,14 +323,12 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
last_prot = 0;
start = -1;
for (l1 = 0; l1 < 4; l1++) {
- cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
- pdpe = le64_to_cpu(pdpe);
+ pdpe = address_space_ldq_le(as, pdp_addr + l1 * 8, attrs, NULL);
end = l1 << 30;
if (pdpe & PG_PRESENT_MASK) {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
- cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
- pde = le64_to_cpu(pde);
+ pde = address_space_ldq_le(as, pd_addr + l2 * 8, attrs, NULL);
end = (l1 << 30) + (l2 << 21);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
@@ -343,8 +338,8 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
- cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
- pte = le64_to_cpu(pte);
+ pte = address_space_ldq_le(as, pt_addr + l3 * 8,
+ attrs, NULL);
end = (l1 << 30) + (l2 << 21) + (l3 << 12);
if (pte & PG_PRESENT_MASK) {
prot = pte & pde & (PG_USER_MASK | PG_RW_MASK |
@@ -373,6 +368,7 @@ static void mem_info_pae32(Monitor *mon, CPUArchState *env, AddressSpace *as)
#ifdef TARGET_X86_64
static void mem_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int prot, last_prot;
uint64_t l1, l2, l3, l4;
uint64_t pml4e, pdpe, pde, pte;
@@ -382,14 +378,12 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as)
last_prot = 0;
start = -1;
for (l1 = 0; l1 < 512; l1++) {
- cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
- pml4e = le64_to_cpu(pml4e);
+ pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
end = l1 << 39;
if (pml4e & PG_PRESENT_MASK) {
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
- cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
- pdpe = le64_to_cpu(pdpe);
+ pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
end = (l1 << 39) + (l2 << 30);
if (pdpe & PG_PRESENT_MASK) {
if (pdpe & PG_PSE_MASK) {
@@ -400,8 +394,8 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as)
} else {
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
- cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
- pde = le64_to_cpu(pde);
+ pde = address_space_ldq_le(as, pd_addr + l3 * 8,
+ attrs, NULL);
end = (l1 << 39) + (l2 << 30) + (l3 << 21);
if (pde & PG_PRESENT_MASK) {
if (pde & PG_PSE_MASK) {
@@ -413,10 +407,10 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as)
} else {
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
- cpu_physical_memory_read(pt_addr
- + l4 * 8,
- &pte, 8);
- pte = le64_to_cpu(pte);
+ pte = address_space_ldq_le(as,
+ pt_addr
+ + l4 * 8,
+ attrs, NULL);
end = (l1 << 39) + (l2 << 30) +
(l3 << 21) + (l4 << 12);
if (pte & PG_PRESENT_MASK) {
@@ -453,6 +447,7 @@ static void mem_info_la48(Monitor *mon, CPUArchState *env, AddressSpace *as)
static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
int prot, last_prot;
uint64_t l0, l1, l2, l3, l4;
uint64_t pml5e, pml4e, pdpe, pde, pte;
@@ -462,8 +457,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
last_prot = 0;
start = -1;
for (l0 = 0; l0 < 512; l0++) {
- cpu_physical_memory_read(pml5_addr + l0 * 8, &pml5e, 8);
- pml5e = le64_to_cpu(pml5e);
+ pml5e = address_space_ldq_le(as, pml5_addr + l0 * 8, attrs, NULL);
end = l0 << 48;
if (!(pml5e & PG_PRESENT_MASK)) {
prot = 0;
@@ -473,8 +467,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
pml4_addr = pml5e & 0x3fffffffff000ULL;
for (l1 = 0; l1 < 512; l1++) {
- cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
- pml4e = le64_to_cpu(pml4e);
+ pml4e = address_space_ldq_le(as, pml4_addr + l1 * 8, attrs, NULL);
end = (l0 << 48) + (l1 << 39);
if (!(pml4e & PG_PRESENT_MASK)) {
prot = 0;
@@ -484,8 +477,7 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
pdp_addr = pml4e & 0x3fffffffff000ULL;
for (l2 = 0; l2 < 512; l2++) {
- cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
- pdpe = le64_to_cpu(pdpe);
+ pdpe = address_space_ldq_le(as, pdp_addr + l2 * 8, attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30);
if (pdpe & PG_PRESENT_MASK) {
prot = 0;
@@ -503,8 +495,8 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
pd_addr = pdpe & 0x3fffffffff000ULL;
for (l3 = 0; l3 < 512; l3++) {
- cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
- pde = le64_to_cpu(pde);
+ pde = address_space_ldq_le(as, pd_addr + l3 * 8,
+ attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30) + (l3 << 21);
if (pde & PG_PRESENT_MASK) {
prot = 0;
@@ -522,8 +514,8 @@ static void mem_info_la57(Monitor *mon, CPUArchState *env, AddressSpace *as)
pt_addr = pde & 0x3fffffffff000ULL;
for (l4 = 0; l4 < 512; l4++) {
- cpu_physical_memory_read(pt_addr + l4 * 8, &pte, 8);
- pte = le64_to_cpu(pte);
+ pte = address_space_ldq_le(as, pt_addr + l4 * 8,
+ attrs, NULL);
end = (l0 << 48) + (l1 << 39) + (l2 << 30) +
(l3 << 21) + (l4 << 12);
if (pte & PG_PRESENT_MASK) {
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL v2 42/79] target/riscv/kvm: Replace legacy cpu_physical_memory_read/write() calls
2025-10-16 15:11 [PULL v2 00/75] Misc single binary patches for 2025-10-16 Philippe Mathieu-Daudé
2025-10-16 15:11 ` [PULL v2 04/79] target/i386/monitor: Propagate CPU address space to 'info mem' handlers Philippe Mathieu-Daudé
2025-10-16 15:11 ` [PULL v2 05/79] target/i386/monitor: Replace legacy cpu_physical_memory_read() calls Philippe Mathieu-Daudé
@ 2025-10-16 15:11 ` Philippe Mathieu-Daudé
2025-10-16 15:11 ` [PULL v2 43/79] target/riscv/monitor: Replace legacy cpu_physical_memory_read() call Philippe Mathieu-Daudé
2025-10-17 15:12 ` [PULL v2 00/75] Misc single binary patches for 2025-10-16 Richard Henderson
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-16 15:11 UTC (permalink / raw)
To: qemu-devel
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Since the SBI DBCN is handled within a vCPU context, use its
default address space. Replace using the address space API.
As with the previous implementation, ignore whether the memory
accesses succeeded or failed.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20251002145742.75624-4-philmd@linaro.org>
---
target/riscv/kvm/kvm-cpu.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index 75ca3fb9fd9..0dd0d59d41a 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -36,6 +36,7 @@
#include "hw/pci/pci.h"
#include "exec/memattrs.h"
#include "system/address-spaces.h"
+#include "system/memory.h"
#include "hw/boards.h"
#include "hw/irq.h"
#include "hw/intc/riscv_imsic.h"
@@ -1564,6 +1565,7 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs)
static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
g_autofree uint8_t *buf = NULL;
RISCVCPU *cpu = RISCV_CPU(cs);
target_ulong num_bytes;
@@ -1602,9 +1604,9 @@ static void kvm_riscv_handle_sbi_dbcn(CPUState *cs, struct kvm_run *run)
exit(1);
}
- cpu_physical_memory_write(addr, buf, ret);
+ address_space_write(cs->as, addr, attrs, buf, ret);
} else {
- cpu_physical_memory_read(addr, buf, num_bytes);
+ address_space_read(cs->as, addr, attrs, buf, num_bytes);
ret = qemu_chr_fe_write_all(serial_hd(0)->be, buf, num_bytes);
if (ret < 0) {
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PULL v2 43/79] target/riscv/monitor: Replace legacy cpu_physical_memory_read() call
2025-10-16 15:11 [PULL v2 00/75] Misc single binary patches for 2025-10-16 Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2025-10-16 15:11 ` [PULL v2 42/79] target/riscv/kvm: Replace legacy cpu_physical_memory_read/write() calls Philippe Mathieu-Daudé
@ 2025-10-16 15:11 ` Philippe Mathieu-Daudé
2025-10-17 15:12 ` [PULL v2 00/75] Misc single binary patches for 2025-10-16 Richard Henderson
4 siblings, 0 replies; 6+ messages in thread
From: Philippe Mathieu-Daudé @ 2025-10-16 15:11 UTC (permalink / raw)
To: qemu-devel
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Propagate the address space to walk_pte(), then replace the
cpu_physical_memory_read() by address_space_read(). Since the
monitor command are run with a vCPU context, use its default
address space. As with the previous implementation, ignore
whether the memory read succeeded or failed.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Message-Id: <20251002145742.75624-5-philmd@linaro.org>
---
target/riscv/monitor.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c
index 100005ea4e9..8a77476db93 100644
--- a/target/riscv/monitor.c
+++ b/target/riscv/monitor.c
@@ -23,6 +23,7 @@
#include "cpu_bits.h"
#include "monitor/monitor.h"
#include "monitor/hmp-target.h"
+#include "system/memory.h"
#ifdef TARGET_RISCV64
#define PTE_HEADER_FIELDS "vaddr paddr "\
@@ -77,11 +78,13 @@ static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr,
attr & PTE_D ? 'd' : '-');
}
-static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
+static void walk_pte(Monitor *mon, AddressSpace *as,
+ hwaddr base, target_ulong start,
int level, int ptidxbits, int ptesize, int va_bits,
target_ulong *vbase, hwaddr *pbase, hwaddr *last_paddr,
target_ulong *last_size, int *last_attr)
{
+ const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
hwaddr pte_addr;
hwaddr paddr;
target_ulong last_start = -1;
@@ -100,7 +103,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
for (idx = 0; idx < (1UL << ptidxbits); idx++) {
pte_addr = base + idx * ptesize;
- cpu_physical_memory_read(pte_addr, &pte, ptesize);
+ address_space_read(as, pte_addr, attrs, &pte, ptesize);
paddr = (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT;
attr = pte & 0xff;
@@ -132,7 +135,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
*last_size = pgsize;
} else {
/* pointer to the next level of the page table */
- walk_pte(mon, paddr, start, level - 1, ptidxbits, ptesize,
+ walk_pte(mon, as, paddr, start, level - 1, ptidxbits, ptesize,
va_bits, vbase, pbase, last_paddr,
last_size, last_attr);
}
@@ -145,6 +148,7 @@ static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
static void mem_info_svxx(Monitor *mon, CPUArchState *env)
{
+ AddressSpace *as = env_cpu(env)->as;
int levels, ptidxbits, ptesize, vm, va_bits;
hwaddr base;
target_ulong vbase;
@@ -199,7 +203,7 @@ static void mem_info_svxx(Monitor *mon, CPUArchState *env)
last_attr = 0;
/* walk page tables, starting from address 0 */
- walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
+ walk_pte(mon, as, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
&vbase, &pbase, &last_paddr, &last_size, &last_attr);
/* don't forget the last one */
--
2.51.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PULL v2 00/75] Misc single binary patches for 2025-10-16
2025-10-16 15:11 [PULL v2 00/75] Misc single binary patches for 2025-10-16 Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2025-10-16 15:11 ` [PULL v2 43/79] target/riscv/monitor: Replace legacy cpu_physical_memory_read() call Philippe Mathieu-Daudé
@ 2025-10-17 15:12 ` Richard Henderson
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2025-10-17 15:12 UTC (permalink / raw)
To: qemu-devel
On 10/16/25 08:11, Philippe Mathieu-Daudé wrote:
> The following changes since commit 8109ebdb95c45d9062c7e6e7beae0ee571fca4f8:
>
> Merge tag 'pull-loongarch-20251015' ofhttps://github.com/bibo-mao/qemu into staging (2025-10-15 14:49:51 -0700)
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/single-binary-20251016
>
> for you to fetch changes up to 8dd133fa85bb49e2e61c489a566ab8460478dc24:
>
> mailmap: Unify Clément Mathieu--Drif emails (2025-10-16 17:07:52 +0200)
>
> v2: Remove legacy cpu_physical_memory_*() calls
>
> ----------------------------------------------------------------
> Various patches related to single binary work:
>
> - Remove some VMSTATE_UINTTL() uses
> - Replace target_ulong by vaddr / hwaddr / uint[32,64]_t
> - Expand TCGv to TCGv_i32 for 32-bit targets
> - Remove some unnecessary checks on TARGET_LONG_BITS
> - Replace few HOST_BIG_ENDIAN preprocessor #ifdef by compile-time if() check
> - Expand MO_TE to either MO_BE or MO_LE
>
> Also:
>
> - Remove legacy cpu_physical_memory_*() calls
> - Fix HPPA FMPYADD opcode
> - Unify Clément Mathieu--Drif email addresses
> ----------------------------------------------------------------
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
r~
^ permalink raw reply [flat|nested] 6+ messages in thread
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