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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce57cd11sm39929648f8f.5.2025.10.17.01.53.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Oct 2025 01:53:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Cc: Richard Henderson , Helge Deller Subject: [PATCH] target/hppa: Set FPCR exception flag bits for non-trapped exceptions Date: Fri, 17 Oct 2025 09:53:50 +0100 Message-ID: <20251017085350.895681-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when we added the code for setting up the registers correctly on trapping FP exceptions, we accidentally broke the handling of the flag bits for non-trapping exceptions. In update_fr0_op() we incorrectly zero out the flag bits and the C bit, so any fp operation would clear previously set flag bits. We also stopped setting the flag bits when the fp operation raises an exception and the trap is not enabled. Adjust the code so that we set the Flag bits for every exception that happened and where the trap is not enabled. (This is the correct behaviour for the case where an instruction triggers two exceptions, one of which traps and one of which does not; that can only happen for inexact + underflow or inexact + overflow.) Cc: qemu-stable@nongnu.org Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158 Signed-off-by: Peter Maydell --- target/hppa/fpu_helper.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 45353202fae..2d272730f60 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -94,7 +94,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) { uint32_t soft_exp = get_float_exception_flags(&env->fp_status); uint32_t hard_exp = 0; - uint32_t shadow = env->fr0_shadow & 0x3ffffff; + uint32_t shadow = env->fr0_shadow; + uint32_t to_flag = 0; uint32_t fr1 = 0; if (likely(soft_exp == 0)) { @@ -122,6 +123,10 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) fr1 |= hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); } } + /* Set the Flag bits for every exception that was not enabled */ + to_flag = hard_exp & ~shadow; + shadow |= to_flag << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); + env->fr0_shadow = shadow; env->fr[0] = (uint64_t)shadow << 32 | fr1; -- 2.43.0