* [PULL 1/9] gitlab: Stop cross-testing for 32-bit MIPS hosts
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 18:28 ` [PULL 2/9] buildsys: Remove support " Richard Henderson
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Thomas Huth
From: Philippe Mathieu-Daudé <philmd@linaro.org>
32-bit host support is deprecated since commit 6d701c9bac1
("meson: Deprecate 32-bit host support"). Next commits will
remove support for 32-bit MIPS hosts. Stop cross-building
QEMU on our CI.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-3-philmd@linaro.org>
---
.gitlab-ci.d/container-cross.yml | 6 ------
.gitlab-ci.d/crossbuilds.yml | 14 --------------
2 files changed, 20 deletions(-)
diff --git a/.gitlab-ci.d/container-cross.yml b/.gitlab-ci.d/container-cross.yml
index 8d3be53b75..0fd7341afa 100644
--- a/.gitlab-ci.d/container-cross.yml
+++ b/.gitlab-ci.d/container-cross.yml
@@ -52,12 +52,6 @@ mips64el-debian-cross-container:
variables:
NAME: debian-mips64el-cross
-mipsel-debian-cross-container:
- extends: .container_job_template
- stage: containers
- variables:
- NAME: debian-mipsel-cross
-
ppc64el-debian-cross-container:
extends: .container_job_template
stage: containers
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml
index 8ff0c27f74..99dfa7eea6 100644
--- a/.gitlab-ci.d/crossbuilds.yml
+++ b/.gitlab-ci.d/crossbuilds.yml
@@ -68,20 +68,6 @@ cross-i686-tci:
# would otherwise be using a parallelism of 9.
MAKE_CHECK_ARGS: check check-tcg -j2
-cross-mipsel-system:
- extends: .cross_system_build_job
- needs:
- - job: mipsel-debian-cross-container
- variables:
- IMAGE: debian-mipsel-cross
-
-cross-mipsel-user:
- extends: .cross_user_build_job
- needs:
- - job: mipsel-debian-cross-container
- variables:
- IMAGE: debian-mipsel-cross
-
cross-mips64el-system:
extends: .cross_system_build_job
needs:
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PULL 2/9] buildsys: Remove support for 32-bit MIPS hosts
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
2025-10-19 18:28 ` [PULL 1/9] gitlab: Stop cross-testing for 32-bit MIPS hosts Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 18:28 ` [PULL 3/9] kvm/mips: Remove support for 32-bit hosts Richard Henderson
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Thomas Huth
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Stop detecting 32-bit MIPS host as supported, update the
deprecation document. See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-8-philmd@linaro.org>
---
configure | 7 -------
docs/about/deprecated.rst | 13 +++++--------
docs/about/removed-features.rst | 6 ++++++
3 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/configure b/configure
index 461b53dd60..8263f81370 100755
--- a/configure
+++ b/configure
@@ -404,8 +404,6 @@ elif check_define _ARCH_PPC ; then
elif check_define __mips__ ; then
if check_define __mips64 ; then
cpu="mips64"
- else
- cpu="mips"
fi
elif check_define __s390__ ; then
if check_define __s390x__ ; then
@@ -473,11 +471,6 @@ case "$cpu" in
host_arch=mips
linux_arch=mips
;;
- mips*)
- cpu=mips
- host_arch=mips
- linux_arch=mips
- ;;
ppc)
host_arch=ppc
diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
index 98361f5832..dacf2882e4 100644
--- a/docs/about/deprecated.rst
+++ b/docs/about/deprecated.rst
@@ -172,17 +172,14 @@ This argument has always been ignored.
Host Architectures
------------------
-Big endian MIPS since 7.2; 32-bit little endian MIPS since 9.2, MIPS since 11.0
-'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
+MIPS (since 11.0)
+'''''''''''''''''
-As Debian 10 ("Buster") moved into LTS the big endian 32 bit version of
-MIPS moved out of support making it hard to maintain our
-cross-compilation CI tests of the architecture. As we no longer have
-CI coverage support may bitrot away before the deprecation process
+MIPS is not supported by Debian 13 ("Trixie") and newer, making it hard to
+maintain our cross-compilation CI tests of the architecture. As we no longer
+have CI coverage support may bitrot away before the deprecation process
completes.
-Likewise, MIPS is not supported by Debian 13 ("Trixie") and newer.
-
System emulation on 32-bit x86 hosts (since 8.0)
''''''''''''''''''''''''''''''''''''''''''''''''
diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
index a5338e44c2..53829f59e6 100644
--- a/docs/about/removed-features.rst
+++ b/docs/about/removed-features.rst
@@ -896,6 +896,12 @@ work around the atomicity issues in system mode by running all vCPUs
in a single thread context; in user mode atomicity was simply broken.
From 10.0, QEMU has disabled configuration of 64-bit guests on 32-bit hosts.
+32-bit MIPS (since 11.0)
+''''''''''''''''''''''''
+
+Debian 12 "Bookworm" removed support for 32-bit MIPS, making it hard to
+maintain our cross-compilation CI tests of the architecture.
+
Guest Emulator ISAs
-------------------
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PULL 3/9] kvm/mips: Remove support for 32-bit hosts
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
2025-10-19 18:28 ` [PULL 1/9] gitlab: Stop cross-testing for 32-bit MIPS hosts Richard Henderson
2025-10-19 18:28 ` [PULL 2/9] buildsys: Remove support " Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 18:28 ` [PULL 4/9] tcg/mips: Remove support for O32 and N32 ABIs Richard Henderson
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Thomas Huth
From: Philippe Mathieu-Daudé <philmd@linaro.org>
See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-7-philmd@linaro.org>
---
meson.build | 2 --
1 file changed, 2 deletions(-)
diff --git a/meson.build b/meson.build
index afaefa0172..c5710a6a47 100644
--- a/meson.build
+++ b/meson.build
@@ -295,8 +295,6 @@ elif cpu == 'ppc'
kvm_targets = ['ppc-softmmu']
elif cpu == 'ppc64'
kvm_targets = ['ppc-softmmu', 'ppc64-softmmu']
-elif cpu == 'mips'
- kvm_targets = ['mips-softmmu', 'mipsel-softmmu']
elif cpu == 'mips64'
kvm_targets = ['mips-softmmu', 'mipsel-softmmu', 'mips64-softmmu', 'mips64el-softmmu']
elif cpu == 'riscv32'
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PULL 4/9] tcg/mips: Remove support for O32 and N32 ABIs
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2025-10-19 18:28 ` [PULL 3/9] kvm/mips: Remove support for 32-bit hosts Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 18:28 ` [PULL 5/9] tcg/mips: Remove support for 32-bit hosts Richard Henderson
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Thomas Huth
From: Philippe Mathieu-Daudé <philmd@linaro.org>
See previous commit for rationale.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-5-philmd@linaro.org>
---
tcg/mips/tcg-target-reg-bits.h | 8 ++----
common-user/host/mips/safe-syscall.inc.S | 35 ------------------------
tcg/mips/tcg-target.c.inc | 26 ++++--------------
3 files changed, 9 insertions(+), 60 deletions(-)
diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h
index 56fe0a725e..ee346a3f25 100644
--- a/tcg/mips/tcg-target-reg-bits.h
+++ b/tcg/mips/tcg-target-reg-bits.h
@@ -7,12 +7,10 @@
#ifndef TCG_TARGET_REG_BITS_H
#define TCG_TARGET_REG_BITS_H
-#if _MIPS_SIM == _ABIO32
-# define TCG_TARGET_REG_BITS 32
-#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
-# define TCG_TARGET_REG_BITS 64
-#else
+#if !defined(_MIPS_SIM) || _MIPS_SIM != _ABI64
# error "Unknown ABI"
#endif
+#define TCG_TARGET_REG_BITS 64
+
#endif
diff --git a/common-user/host/mips/safe-syscall.inc.S b/common-user/host/mips/safe-syscall.inc.S
index 6a44614970..3b196cc634 100644
--- a/common-user/host/mips/safe-syscall.inc.S
+++ b/common-user/host/mips/safe-syscall.inc.S
@@ -30,15 +30,9 @@
* arguments being syscall arguments (also 'long').
*/
-#if _MIPS_SIM == _ABIO32
-/* 8 * 4 = 32 for outgoing parameters; 1 * 4 for s0 save; 1 * 4 for align. */
-#define FRAME 40
-#define OFS_S0 32
-#else
/* 1 * 8 for s0 save; 1 * 8 for align. */
#define FRAME 16
#define OFS_S0 0
-#endif
NESTED(safe_syscall_base, FRAME, ra)
@@ -47,34 +41,6 @@ NESTED(safe_syscall_base, FRAME, ra)
.cfi_adjust_cfa_offset FRAME
REG_S s0, OFS_S0(sp)
.cfi_rel_offset s0, OFS_S0
-#if _MIPS_SIM == _ABIO32
- /*
- * The syscall calling convention is nearly the same as C:
- * we enter with a0 == &signal_pending
- * a1 == syscall number
- * a2, a3, stack == syscall arguments
- * and return the result in a0
- * and the syscall instruction needs
- * v0 == syscall number
- * a0 ... a3, stack == syscall arguments
- * and returns the result in v0
- * Shuffle everything around appropriately.
- */
- move s0, a0 /* signal_pending pointer */
- move v0, a1 /* syscall number */
- move a0, a2 /* syscall arguments */
- move a1, a3
- lw a2, FRAME+16(sp)
- lw a3, FRAME+20(sp)
- lw t4, FRAME+24(sp)
- lw t5, FRAME+28(sp)
- lw t6, FRAME+32(sp)
- lw t7, FRAME+40(sp)
- sw t4, 16(sp)
- sw t5, 20(sp)
- sw t6, 24(sp)
- sw t7, 28(sp)
-#else
/*
* The syscall calling convention is nearly the same as C:
* we enter with a0 == &signal_pending
@@ -95,7 +61,6 @@ NESTED(safe_syscall_base, FRAME, ra)
move a3, a5
move a4, a6
move a5, a7
-#endif
/*
* This next sequence of code works in conjunction with the
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 400eafbab4..4d9d029844 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -26,16 +26,10 @@
/* used for function call generation */
#define TCG_TARGET_STACK_ALIGN 16
-#if _MIPS_SIM == _ABIO32
-# define TCG_TARGET_CALL_STACK_OFFSET 16
-# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN
-# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF
-#else
-# define TCG_TARGET_CALL_STACK_OFFSET 0
-# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
-# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
-#endif
+#define TCG_TARGET_CALL_STACK_OFFSET 0
#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
+#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL
+#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
#if TCG_TARGET_REG_BITS == 32
@@ -135,12 +129,10 @@ static const TCGReg tcg_target_call_iarg_regs[] = {
TCG_REG_A1,
TCG_REG_A2,
TCG_REG_A3,
-#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
TCG_REG_T0,
TCG_REG_T1,
TCG_REG_T2,
TCG_REG_T3,
-#endif
};
static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
@@ -1053,17 +1045,11 @@ static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
* Note that __mips_abicalls requires the called function's address
* to be loaded into $25 (t9), even if a direct branch is in range.
*
- * For n64, always drop the pointer into the constant pool.
- * We can re-use helper addresses often and do not want any
- * of the longer sequences tcg_out_movi may try.
+ * We can re-use helper addresses often; always drop the pointer
+ * into the constant pool.
*/
- if (sizeof(uintptr_t) == 8) {
- tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB);
- } else {
- tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg);
- }
+ tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB);
- /* But do try a direct branch, allowing the cpu better insn prefetch. */
if (tail) {
if (!tcg_out_opc_jmp(s, OPC_J, arg)) {
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0);
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PULL 5/9] tcg/mips: Remove support for 32-bit hosts
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2025-10-19 18:28 ` [PULL 4/9] tcg/mips: Remove support for O32 and N32 ABIs Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 18:28 ` [PULL 6/9] tcg/mips: Remove ALIAS_PADD, ALIAS_PADDI Richard Henderson
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Thomas Huth
From: Philippe Mathieu-Daudé <philmd@linaro.org>
32-bit host support is deprecated since commit 6d701c9bac1
("meson: Deprecate 32-bit host support"), released as v10.0.
The next release being v10.2, we can remove the TCG backend
for 32-bit MIPS hosts.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251009195210.33161-6-philmd@linaro.org>
---
tcg/mips/tcg-target-has.h | 2 -
tcg/mips/tcg-target.c.inc | 285 +++++---------------------------------
2 files changed, 38 insertions(+), 249 deletions(-)
diff --git a/tcg/mips/tcg-target-has.h b/tcg/mips/tcg-target-has.h
index b9eb338528..88f0145efb 100644
--- a/tcg/mips/tcg-target-has.h
+++ b/tcg/mips/tcg-target-has.h
@@ -39,11 +39,9 @@ extern bool use_mips32r2_instructions;
#endif
/* optional instructions */
-#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_extr_i64_i32 1
#define TCG_TARGET_HAS_ext32s_i64 1
#define TCG_TARGET_HAS_ext32u_i64 1
-#endif
/* optional instructions detected at runtime */
#define TCG_TARGET_HAS_qemu_ldst_i128 0
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 4d9d029844..51a15705cb 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -32,15 +32,6 @@
#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN
-#if TCG_TARGET_REG_BITS == 32
-# define LO_OFF (HOST_BIG_ENDIAN * 4)
-# define HI_OFF (4 - LO_OFF)
-#else
-/* Assert at compile-time that these values are never used for 64-bit. */
-# define LO_OFF ({ qemu_build_not_reached(); 0; })
-# define HI_OFF ({ qemu_build_not_reached(); 0; })
-#endif
-
#ifdef CONFIG_DEBUG_TCG
static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"zero",
@@ -84,11 +75,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
#define TCG_TMP3 TCG_REG_T7
#define TCG_GUEST_BASE_REG TCG_REG_S7
-#if TCG_TARGET_REG_BITS == 64
#define TCG_REG_TB TCG_REG_S6
-#else
-#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; })
-#endif
/* check if we really need so many registers :P */
static const int tcg_target_reg_alloc_order[] = {
@@ -559,7 +546,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
tcg_target_long tmp;
int sh, lo;
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ if (type == TCG_TYPE_I32) {
arg = (int32_t)arg;
}
@@ -567,7 +554,6 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
if (tcg_out_movi_two(s, ret, arg)) {
return;
}
- assert(TCG_TARGET_REG_BITS == 64);
/* Load addresses within 2GB of TB with 1 or 3 insns. */
tmp = tcg_tbrel_diff(s, (void *)arg);
@@ -630,8 +616,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
static void tcg_out_movi(TCGContext *s, TCGType type,
TCGReg ret, tcg_target_long arg)
{
- TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0;
- tcg_out_movi_int(s, type, ret, arg, tbreg);
+ tcg_out_movi_int(s, type, ret, arg, TCG_REG_TB);
}
static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs)
@@ -658,7 +643,6 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs)
static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs)
{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0);
}
@@ -701,7 +685,6 @@ static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub)
static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
if (use_mips32r2_instructions) {
tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0);
} else {
@@ -727,20 +710,14 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
TCGReg arg1, intptr_t arg2)
{
- MIPSInsn opc = OPC_LD;
- if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
- opc = OPC_LW;
- }
+ MIPSInsn opc = type == TCG_TYPE_I32 ? OPC_LW : OPC_LD;
tcg_out_ldst(s, opc, arg, arg1, arg2);
}
static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
TCGReg arg1, intptr_t arg2)
{
- MIPSInsn opc = OPC_SD;
- if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) {
- opc = OPC_SW;
- }
+ MIPSInsn opc = type == TCG_TYPE_I32 ? OPC_SW : OPC_SD;
tcg_out_ldst(s, opc, arg, arg1, arg2);
}
@@ -918,72 +895,6 @@ void tcg_out_br(TCGContext *s, TCGLabel *l)
tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, l);
}
-static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh)
-{
- int flags = 0;
-
- switch (cond) {
- case TCG_COND_EQ:
- flags |= SETCOND_INV;
- /* fall through */
- case TCG_COND_NE:
- flags |= SETCOND_NEZ;
- tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl);
- tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh);
- tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1);
- break;
-
- default:
- tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh);
- tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond),
- TCG_TMP1, al, bl);
- tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0);
- tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh);
- tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1);
- break;
- }
- return ret | flags;
-}
-
-static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg al, TCGReg ah,
- TCGArg bl, bool const_bl,
- TCGArg bh, bool const_bh)
-{
- int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh);
- tcg_out_setcond_end(s, ret, tmpflags);
-}
-
-#if TCG_TARGET_REG_BITS != 32
-__attribute__((unused))
-#endif
-static const TCGOutOpSetcond2 outop_setcond2 = {
- .base.static_constraint = C_O1_I4(r, r, r, rz, rz),
- .out = tgen_setcond2,
-};
-
-static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
- TCGArg bl, bool const_bl,
- TCGArg bh, bool const_bh, TCGLabel *l)
-{
- int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh);
- TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
- MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE;
-
- tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0);
- tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO);
- tcg_out_nop(s);
-}
-
-#if TCG_TARGET_REG_BITS != 32
-__attribute__((unused))
-#endif
-static const TCGOutOpBrcond2 outop_brcond2 = {
- .base.static_constraint = C_O0_I4(r, r, rz, rz),
- .out = tgen_brcond2,
-};
-
static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond,
TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2,
TCGArg v1, bool const_v1, TCGArg v2, bool const_v2)
@@ -1183,7 +1094,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off);
/* Extract the TLB index from the address into TMP3. */
- if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) {
+ if (addr_type == TCG_TYPE_I32) {
tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr,
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
} else {
@@ -1195,7 +1106,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
/* Load the tlb comparator. */
- if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
+ if (addr_type == TCG_TYPE_I32) {
tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3,
cmp_off + HOST_BIG_ENDIAN * 4);
} else {
@@ -1212,8 +1123,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
*/
tcg_out_movi(s, addr_type, TCG_TMP1, TARGET_PAGE_MASK | a_mask);
if (a_mask < s_mask) {
- tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32
- || addr_type == TCG_TYPE_I32
+ tcg_out_opc_imm(s, (addr_type == TCG_TYPE_I32
? OPC_ADDIU : OPC_DADDIU),
TCG_TMP2, addr, s_mask - a_mask);
tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2);
@@ -1222,7 +1132,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
}
/* Zero extend a 32-bit guest address for a 64-bit host. */
- if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
+ if (addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_TMP2, addr);
addr = TCG_TMP2;
}
@@ -1255,7 +1165,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
}
base = addr;
- if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
+ if (addr_type == TCG_TYPE_I32) {
tcg_out_ext32u(s, TCG_REG_A0, base);
base = TCG_REG_A0;
}
@@ -1291,7 +1201,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_LH, lo, base, 0);
break;
case MO_UL:
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) {
+ if (type == TCG_TYPE_I64) {
tcg_out_opc_imm(s, OPC_LWU, lo, base, 0);
break;
}
@@ -1300,16 +1210,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_LW, lo, base, 0);
break;
case MO_UQ:
- /* Prefer to load from offset 0 first, but allow for overlap. */
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
- } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) {
- tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
- tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
- } else {
- tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF);
- tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF);
- }
+ tcg_out_opc_imm(s, OPC_LD, lo, base, 0);
break;
default:
g_assert_not_reached();
@@ -1351,21 +1252,14 @@ static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
case MO_32:
tcg_out_opc_imm(s, lw1, lo, base, 0);
tcg_out_opc_imm(s, lw2, lo, base, 3);
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) {
+ if (type == TCG_TYPE_I64 && !sgn) {
tcg_out_ext32u(s, lo, lo);
}
break;
case MO_64:
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_opc_imm(s, ld1, lo, base, 0);
- tcg_out_opc_imm(s, ld2, lo, base, 7);
- } else {
- tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
- tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
- tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
- tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
- }
+ tcg_out_opc_imm(s, ld1, lo, base, 0);
+ tcg_out_opc_imm(s, ld2, lo, base, 7);
break;
default:
@@ -1401,36 +1295,8 @@ static const TCGOutOpQemuLdSt outop_qemu_ld = {
.out = tgen_qemu_ld,
};
-static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo,
- TCGReg datahi, TCGReg addr, MemOpIdx oi)
-{
- MemOp opc = get_memop(oi);
- TCGLabelQemuLdst *ldst;
- HostAddress h;
-
- tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
- ldst = prepare_host_addr(s, &h, addr, oi, true);
-
- if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
- tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, type);
- } else {
- tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, type);
- }
-
- if (ldst) {
- ldst->type = type;
- ldst->datalo_reg = datalo;
- ldst->datahi_reg = datahi;
- ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
- }
-}
-
static const TCGOutOpQemuLdSt2 outop_qemu_ld2 = {
- /* Ensure that the mips32 code is compiled but discarded for mips64. */
- .base.static_constraint =
- TCG_TARGET_REG_BITS == 32 ? C_O2_I1(r, r, r) : C_NotImplemented,
- .out =
- TCG_TARGET_REG_BITS == 32 ? tgen_qemu_ld2 : NULL,
+ .base.static_constraint = C_NotImplemented,
};
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
@@ -1447,12 +1313,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
tcg_out_opc_imm(s, OPC_SW, lo, base, 0);
break;
case MO_64:
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
- } else {
- tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0);
- tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4);
- }
+ tcg_out_opc_imm(s, OPC_SD, lo, base, 0);
break;
default:
g_assert_not_reached();
@@ -1480,15 +1341,8 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
break;
case MO_64:
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_opc_imm(s, sd1, lo, base, 0);
- tcg_out_opc_imm(s, sd2, lo, base, 7);
- } else {
- tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0);
- tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3);
- tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0);
- tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3);
- }
+ tcg_out_opc_imm(s, sd1, lo, base, 0);
+ tcg_out_opc_imm(s, sd2, lo, base, 7);
break;
default:
@@ -1524,36 +1378,8 @@ static const TCGOutOpQemuLdSt outop_qemu_st = {
.out = tgen_qemu_st,
};
-static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo,
- TCGReg datahi, TCGReg addr, MemOpIdx oi)
-{
- MemOp opc = get_memop(oi);
- TCGLabelQemuLdst *ldst;
- HostAddress h;
-
- tcg_debug_assert(TCG_TARGET_REG_BITS == 32);
- ldst = prepare_host_addr(s, &h, addr, oi, false);
-
- if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) {
- tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc);
- } else {
- tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc);
- }
-
- if (ldst) {
- ldst->type = type;
- ldst->datalo_reg = datalo;
- ldst->datahi_reg = datahi;
- ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
- }
-}
-
static const TCGOutOpQemuLdSt2 outop_qemu_st2 = {
- /* Ensure that the mips32 code is compiled but discarded for mips64. */
- .base.static_constraint =
- TCG_TARGET_REG_BITS == 32 ? C_O0_I3(rz, rz, r) : C_NotImplemented,
- .out =
- TCG_TARGET_REG_BITS == 32 ? tgen_qemu_st2 : NULL,
+ .base.static_constraint = C_NotImplemented,
};
static void tcg_out_mb(TCGContext *s, unsigned a0)
@@ -1578,22 +1404,14 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
int16_t lo = 0;
if (a0) {
- intptr_t ofs;
- if (TCG_TARGET_REG_BITS == 64) {
- ofs = tcg_tbrel_diff(s, (void *)a0);
- lo = ofs;
- if (ofs == lo) {
- base = TCG_REG_TB;
- } else {
- base = TCG_REG_V0;
- tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
- tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB);
- }
+ intptr_t ofs = tcg_tbrel_diff(s, (void *)a0);
+ lo = ofs;
+ if (ofs == lo) {
+ base = TCG_REG_TB;
} else {
- ofs = a0;
- lo = ofs;
base = TCG_REG_V0;
tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
+ tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB);
}
}
if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
@@ -1610,35 +1428,24 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
TCGReg base, dest;
/* indirect jump method */
- if (TCG_TARGET_REG_BITS == 64) {
- dest = TCG_REG_TB;
- base = TCG_REG_TB;
- ofs = tcg_tbrel_diff(s, (void *)ofs);
- } else {
- dest = TCG_TMP0;
- base = TCG_REG_ZERO;
- }
+ dest = TCG_REG_TB;
+ base = TCG_REG_TB;
+ ofs = tcg_tbrel_diff(s, (void *)ofs);
tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs);
tcg_out_opc_reg(s, OPC_JR, 0, dest, 0);
/* delay slot */
tcg_out_nop(s);
set_jmp_reset_offset(s, which);
- if (TCG_TARGET_REG_BITS == 64) {
- /* For the unlinked case, need to reset TCG_REG_TB. */
- tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB,
- -tcg_current_code_size(s));
- }
+ /* For the unlinked case, need to reset TCG_REG_TB. */
+ tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB,
+ -tcg_current_code_size(s));
}
static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0)
{
tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
- } else {
- tcg_out_nop(s);
- }
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0);
}
void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
@@ -1833,7 +1640,6 @@ static const TCGOutOpBinary outop_eqv = {
.base.static_constraint = C_NotImplemented,
};
-#if TCG_TARGET_REG_BITS == 64
static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1)
{
tcg_out_dsra(s, a0, a1, 32);
@@ -1843,7 +1649,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extrh_i64_i32,
};
-#endif
static void tgen_mul(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
@@ -2232,7 +2037,6 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32,
};
-#if TCG_TARGET_REG_BITS == 64
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
{
if (use_mips32r2_instructions) {
@@ -2250,7 +2054,6 @@ static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap64,
};
-#endif /* TCG_TARGET_REG_BITS == 64 */
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
@@ -2378,7 +2181,6 @@ static const TCGOutOpLoad outop_ld16s = {
.out = tgen_ld16s,
};
-#if TCG_TARGET_REG_BITS == 64
static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest,
TCGReg base, ptrdiff_t offset)
{
@@ -2400,7 +2202,6 @@ static const TCGOutOpLoad outop_ld32s = {
.base.static_constraint = C_O1_I1(r, r),
.out = tgen_ld32s,
};
-#endif
static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data,
TCGReg base, ptrdiff_t offset)
@@ -2539,7 +2340,7 @@ static tcg_insn_unit *align_code_ptr(TCGContext *s)
}
/* Stack frame parameters. */
-#define REG_SIZE (TCG_TARGET_REG_BITS / 8)
+#define REG_SIZE 8
#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
@@ -2571,17 +2372,15 @@ static void tcg_target_qemu_prologue(TCGContext *s)
* with the address of the prologue, so we can use that instead
* of TCG_REG_TB.
*/
-#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls)
+#if !defined(__mips_abicalls)
# error "Unknown mips abi"
#endif
tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base,
- TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0);
+ TCG_REG_T9);
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
}
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
- }
+ tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]);
/* Call generated code */
tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0);
@@ -2637,10 +2436,6 @@ static void tcg_target_qemu_prologue(TCGContext *s)
/* t3 = dcba -- delay slot */
tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1);
- if (TCG_TARGET_REG_BITS == 32) {
- return;
- }
-
/*
* bswap32u -- unsigned 32-bit swap. a0 = ....abcd.
*/
@@ -2735,9 +2530,7 @@ static void tcg_target_init(TCGContext *s)
{
tcg_target_detect_isa();
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff;
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
- }
+ tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff;
tcg_target_call_clobber_regs = 0;
tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0);
@@ -2768,9 +2561,7 @@ static void tcg_target_init(TCGContext *s)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */
tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */
- if (TCG_TARGET_REG_BITS == 64) {
- tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */
- }
+ tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */
}
typedef struct {
@@ -2788,7 +2579,7 @@ static const DebugFrame debug_frame = {
.h.cie.id = -1,
.h.cie.version = 1,
.h.cie.code_align = 1,
- .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
+ .h.cie.data_align = -REG_SIZE & 0x7f, /* sleb128 */
.h.cie.return_column = TCG_REG_RA,
/* Total FDE size does not include the "len" member. */
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PULL 6/9] tcg/mips: Remove ALIAS_PADD, ALIAS_PADDI
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
` (4 preceding siblings ...)
2025-10-19 18:28 ` [PULL 5/9] tcg/mips: Remove support for 32-bit hosts Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 18:28 ` [PULL 7/9] buildsys: Remove support for 32-bit PPC hosts Richard Henderson
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Thomas Huth, Philippe Mathieu-Daudé
These aliases existed to simplify code for O32 and N32.
Now that the 64-bit abi is the only one supported, we
can use the DADD* instructions directly.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target.c.inc | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 51a15705cb..60c703a093 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -340,10 +340,6 @@ typedef enum {
OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6,
OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6,
OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6,
-
- /* Aliases for convenience. */
- ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU,
- ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU,
} MIPSInsn;
/*
@@ -700,7 +696,7 @@ static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
if (ofs != lo) {
tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo);
if (addr != TCG_REG_ZERO) {
- tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr);
+ tcg_out_opc_reg(s, OPC_DADDU, TCG_TMP0, TCG_TMP0, addr);
}
addr = TCG_TMP0;
}
@@ -1103,7 +1099,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0);
/* Add the tlb_table pointer, creating the CPUTLBEntry address. */
- tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1);
+ tcg_out_opc_reg(s, OPC_DADDU, TCG_TMP3, TCG_TMP3, TCG_TMP1);
/* Load the tlb comparator. */
if (addr_type == TCG_TYPE_I32) {
@@ -1142,7 +1138,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
/* delay slot */
base = TCG_TMP3;
- tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr);
+ tcg_out_opc_reg(s, OPC_DADDU, base, TCG_TMP3, addr);
} else {
if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) {
ldst = new_ldst_label(s);
@@ -1171,9 +1167,9 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
}
if (guest_base) {
if (guest_base == (int16_t)guest_base) {
- tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base);
+ tcg_out_opc_imm(s, OPC_DADDIU, TCG_REG_A0, base, guest_base);
} else {
- tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base,
+ tcg_out_opc_reg(s, OPC_DADDU, TCG_REG_A0, base,
TCG_GUEST_BASE_REG);
}
base = TCG_REG_A0;
@@ -1411,7 +1407,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
} else {
base = TCG_REG_V0;
tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo);
- tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB);
+ tcg_out_opc_reg(s, OPC_DADDU, base, base, TCG_REG_TB);
}
}
if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) {
@@ -1419,7 +1415,7 @@ static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0);
}
/* delay slot */
- tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo);
+ tcg_out_opc_imm(s, OPC_DADDIU, TCG_REG_V0, base, lo);
}
static void tcg_out_goto_tb(TCGContext *s, int which)
@@ -1438,7 +1434,7 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
set_jmp_reset_offset(s, which);
/* For the unlinked case, need to reset TCG_REG_TB. */
- tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB,
+ tcg_out_ldst(s, OPC_DADDIU, TCG_REG_TB, TCG_REG_TB,
-tcg_current_code_size(s));
}
@@ -2360,7 +2356,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
/* TB prologue */
- tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
+ tcg_out_opc_imm(s, OPC_DADDIU, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
@@ -2403,7 +2399,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0);
/* delay slot */
- tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
+ tcg_out_opc_imm(s, OPC_DADDIU, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
if (use_mips32r2_instructions) {
return;
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PULL 7/9] buildsys: Remove support for 32-bit PPC hosts
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
` (5 preceding siblings ...)
2025-10-19 18:28 ` [PULL 6/9] tcg/mips: Remove ALIAS_PADD, ALIAS_PADDI Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 18:28 ` [PULL 8/9] tcg/ppc: Remove dead cases from tcg_target_op_def Richard Henderson
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé, Thomas Huth
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Stop detecting 32-bit PPC host as supported.
See previous commit for rationale.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[rth: Retain _ARCH_PPC64 check in udiv_qrnnd]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251014173900.87497-4-philmd@linaro.org>
---
include/qemu/timer.h | 13 +------------
disas/disas-host.c | 4 +---
util/cacheflush.c | 4 ++--
configure | 19 +++++--------------
4 files changed, 9 insertions(+), 31 deletions(-)
diff --git a/include/qemu/timer.h b/include/qemu/timer.h
index aec730ac25..406d741120 100644
--- a/include/qemu/timer.h
+++ b/include/qemu/timer.h
@@ -850,12 +850,11 @@ static inline int64_t get_clock(void)
/*******************************************/
/* host CPU ticks (if available) */
-#if defined(_ARCH_PPC)
+#if defined(_ARCH_PPC64)
static inline int64_t cpu_get_host_ticks(void)
{
int64_t retval;
-#ifdef _ARCH_PPC64
/* This reads timebase in one 64bit go and includes Cell workaround from:
http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html
*/
@@ -863,16 +862,6 @@ static inline int64_t cpu_get_host_ticks(void)
"cmpwi %0,0\n\t"
"beq- $-8"
: "=r" (retval));
-#else
- /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */
- unsigned long junk;
- __asm__ __volatile__ ("mfspr %1,269\n\t" /* mftbu */
- "mfspr %L0,268\n\t" /* mftb */
- "mfspr %0,269\n\t" /* mftbu */
- "cmpw %0,%1\n\t"
- "bne $-16"
- : "=r" (retval), "=r" (junk));
-#endif
return retval;
}
diff --git a/disas/disas-host.c b/disas/disas-host.c
index 8146fafe80..4b06f41fa6 100644
--- a/disas/disas-host.c
+++ b/disas/disas-host.c
@@ -56,11 +56,9 @@ static void initialize_debug_host(CPUDebug *s)
s->info.cap_mode = CS_MODE_64;
s->info.cap_insn_unit = 1;
s->info.cap_insn_split = 8;
-#elif defined(_ARCH_PPC)
+#elif defined(_ARCH_PPC64)
s->info.cap_arch = CS_ARCH_PPC;
-# ifdef _ARCH_PPC64
s->info.cap_mode = CS_MODE_64;
-# endif
#elif defined(__riscv)
#if defined(_ILP32) || (__riscv_xlen == 32)
s->info.print_insn = print_insn_riscv32;
diff --git a/util/cacheflush.c b/util/cacheflush.c
index 17c58918de..69c9614e2c 100644
--- a/util/cacheflush.c
+++ b/util/cacheflush.c
@@ -153,7 +153,7 @@ static void arch_cache_info(int *isize, int *dsize)
}
}
-#elif defined(_ARCH_PPC) && defined(__linux__)
+#elif defined(_ARCH_PPC64) && defined(__linux__)
# include "elf.h"
static void arch_cache_info(int *isize, int *dsize)
@@ -187,7 +187,7 @@ static void fallback_cache_info(int *isize, int *dsize)
} else if (*dsize) {
*isize = *dsize;
} else {
-#if defined(_ARCH_PPC)
+#if defined(_ARCH_PPC64)
/*
* For PPC, we're going to use the cache sizes computed for
* flush_idcache_range. Which means that we must use the
diff --git a/configure b/configure
index 8263f81370..a2f66f7ff9 100755
--- a/configure
+++ b/configure
@@ -391,15 +391,11 @@ elif check_define __sparc__ ; then
else
cpu="sparc"
fi
-elif check_define _ARCH_PPC ; then
- if check_define _ARCH_PPC64 ; then
- if check_define _LITTLE_ENDIAN ; then
- cpu="ppc64le"
- else
- cpu="ppc64"
- fi
+elif check_define _ARCH_PPC64 ; then
+ if check_define _LITTLE_ENDIAN ; then
+ cpu="ppc64le"
else
- cpu="ppc"
+ cpu="ppc64"
fi
elif check_define __mips__ ; then
if check_define __mips64 ; then
@@ -472,11 +468,6 @@ case "$cpu" in
linux_arch=mips
;;
- ppc)
- host_arch=ppc
- linux_arch=powerpc
- CPU_CFLAGS="-m32"
- ;;
ppc64)
host_arch=ppc64
linux_arch=powerpc
@@ -1471,7 +1462,7 @@ probe_target_compiler() {
container_image=debian-all-test-cross
container_cross_prefix=mips64-linux-gnuabi64-
;;
- ppc|ppc64|ppc64le)
+ ppc64|ppc64le)
container_image=debian-all-test-cross
container_cross_prefix=powerpc${target_arch#ppc}-linux-gnu-
;;
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PULL 8/9] tcg/ppc: Remove dead cases from tcg_target_op_def
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
` (6 preceding siblings ...)
2025-10-19 18:28 ` [PULL 7/9] buildsys: Remove support for 32-bit PPC hosts Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 18:28 ` [PULL 9/9] tcg/ppc: Remove support for 32-bit hosts Richard Henderson
2025-10-19 19:35 ` [PULL 0/9] tcg patch queue Richard Henderson
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
Missed some lines when converting to TCGOutOpQemuLdSt*.
Fixes: 86fe5c2597c ("tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}")
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.c.inc | 6 ------
1 file changed, 6 deletions(-)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index b8b23d44d5..cd2b68f9e1 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -4435,12 +4435,6 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
{
switch (op) {
- case INDEX_op_qemu_st:
- return C_O0_I2(r, r);
- case INDEX_op_qemu_st2:
- return TCG_TARGET_REG_BITS == 64
- ? C_O0_I3(o, m, r) : C_O0_I3(r, r, r);
-
case INDEX_op_add_vec:
case INDEX_op_sub_vec:
case INDEX_op_mul_vec:
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PULL 9/9] tcg/ppc: Remove support for 32-bit hosts
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
` (7 preceding siblings ...)
2025-10-19 18:28 ` [PULL 8/9] tcg/ppc: Remove dead cases from tcg_target_op_def Richard Henderson
@ 2025-10-19 18:28 ` Richard Henderson
2025-10-19 19:35 ` [PULL 0/9] tcg patch queue Richard Henderson
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 18:28 UTC (permalink / raw)
To: qemu-devel; +Cc: Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <philmd@linaro.org>
32-bit host support is deprecated since commit 6d701c9bac1
("meson: Deprecate 32-bit host support"), released as v10.0.
The next release being v10.2, we can remove the TCG backend
for 32-bit PPC hosts.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20251014173900.87497-2-philmd@linaro.org>
---
tcg/ppc/tcg-target-has.h | 5 +-
tcg/ppc/tcg-target-reg-bits.h | 8 +-
tcg/ppc/tcg-target.c.inc | 385 +++++++---------------------------
3 files changed, 79 insertions(+), 319 deletions(-)
diff --git a/tcg/ppc/tcg-target-has.h b/tcg/ppc/tcg-target-has.h
index 81ec5aece7..a3711feeae 100644
--- a/tcg/ppc/tcg-target-has.h
+++ b/tcg/ppc/tcg-target-has.h
@@ -17,12 +17,9 @@
#define have_vsx (cpuinfo & CPUINFO_VSX)
/* optional instructions */
-#if TCG_TARGET_REG_BITS == 64
#define TCG_TARGET_HAS_extr_i64_i32 0
-#endif
-#define TCG_TARGET_HAS_qemu_ldst_i128 \
- (TCG_TARGET_REG_BITS == 64 && have_isa_2_07)
+#define TCG_TARGET_HAS_qemu_ldst_i128 have_isa_2_07
#define TCG_TARGET_HAS_tst 1
diff --git a/tcg/ppc/tcg-target-reg-bits.h b/tcg/ppc/tcg-target-reg-bits.h
index 0efa80e7e0..3a15d7bee4 100644
--- a/tcg/ppc/tcg-target-reg-bits.h
+++ b/tcg/ppc/tcg-target-reg-bits.h
@@ -7,10 +7,10 @@
#ifndef TCG_TARGET_REG_BITS_H
#define TCG_TARGET_REG_BITS_H
-#ifdef _ARCH_PPC64
-# define TCG_TARGET_REG_BITS 64
-#else
-# define TCG_TARGET_REG_BITS 32
+#ifndef _ARCH_PPC64
+# error Expecting 64-bit host architecture
#endif
+#define TCG_TARGET_REG_BITS 64
+
#endif
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index cd2b68f9e1..3c36b26f25 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -29,35 +29,18 @@
* Apple XCode does not define _CALL_DARWIN.
* Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV or _CALL_AIX.
*/
-#if TCG_TARGET_REG_BITS == 64
-# ifdef _CALL_AIX
+#ifdef _CALL_AIX
/* ok */
-# elif defined(_CALL_ELF) && _CALL_ELF == 1
+#elif defined(_CALL_ELF) && _CALL_ELF == 1
# define _CALL_AIX
-# elif defined(_CALL_ELF) && _CALL_ELF == 2
+#elif defined(_CALL_ELF) && _CALL_ELF == 2
/* ok */
-# else
-# error "Unknown ABI"
-# endif
#else
-# if defined(_CALL_SYSV) || defined(_CALL_DARWIN)
- /* ok */
-# elif defined(__APPLE__)
-# define _CALL_DARWIN
-# elif defined(__ELF__)
-# define _CALL_SYSV
-# else
# error "Unknown ABI"
-# endif
#endif
-#if TCG_TARGET_REG_BITS == 64
-# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND
-# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
-#else
-# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL
-# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF
-#endif
+#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND
+#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL
#ifdef _CALL_SYSV
# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN
# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF
@@ -81,7 +64,7 @@
#define TCG_VEC_TMP2 TCG_REG_V1
#define TCG_REG_TB TCG_REG_R31
-#define USE_REG_TB (TCG_TARGET_REG_BITS == 64 && !have_isa_3_00)
+#define USE_REG_TB !have_isa_3_00
/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
#define SZP ((int)sizeof(void *))
@@ -327,8 +310,7 @@ static bool tcg_target_const_match(int64_t sval, int ct,
if (uval == (uint32_t)uval && mask_operand(uval, &mb, &me)) {
return 1;
}
- if (TCG_TARGET_REG_BITS == 64 &&
- mask64_operand(uval << clz64(uval), &mb, &me)) {
+ if (mask64_operand(uval << clz64(uval), &mb, &me)) {
return 1;
}
return 0;
@@ -857,10 +839,8 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
return true;
}
switch (type) {
- case TCG_TYPE_I64:
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
- /* fallthru */
case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
if (ret < TCG_REG_V0) {
if (arg < TCG_REG_V0) {
tcg_out32(s, OR | SAB(arg, ret, arg));
@@ -898,7 +878,6 @@ static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
static void tcg_out_rld_rc(TCGContext *s, int op, TCGReg ra, TCGReg rs,
int sh, int mb, bool rc)
{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb | rc);
@@ -946,13 +925,11 @@ static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src)
static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src)
{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out32(s, EXTSW | RA(dst) | RS(src));
}
static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_rld(s, RLDICL, dst, src, 0, 32);
}
@@ -968,7 +945,6 @@ static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src)
static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn)
{
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_mov(s, TCG_TYPE_I32, rd, rn);
}
@@ -1037,9 +1013,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
tcg_target_long tmp;
int shift;
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
-
- if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ if (type == TCG_TYPE_I32) {
arg = (int32_t)arg;
}
@@ -1076,7 +1050,7 @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
/* Load 32-bit immediates with two insns. Note that we've already
eliminated bare ADDIS, so we know both insns are required. */
- if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
+ if (arg == (int32_t)arg) {
tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
tcg_out32(s, ORI | SAI(ret, ret, arg));
return;
@@ -1227,19 +1201,10 @@ static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
if (have_vsx) {
load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
- if (TCG_TARGET_REG_BITS == 64) {
- new_pool_label(s, val, rel, s->code_ptr, add);
- } else {
- new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val);
- }
+ new_pool_label(s, val, rel, s->code_ptr, add);
} else {
load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
- if (TCG_TARGET_REG_BITS == 64) {
- new_pool_l2(s, rel, s->code_ptr, add, val, val);
- } else {
- new_pool_l4(s, rel, s->code_ptr, add,
- val >> 32, val, val >> 32, val);
- }
+ new_pool_l2(s, rel, s->code_ptr, add, val, val);
}
if (USE_REG_TB) {
@@ -1351,7 +1316,6 @@ static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
{
int mb, me;
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
if (mask64_operand(c, &mb, &me)) {
if (mb == 0) {
tcg_out_rld(s, RLDICR, dst, src, 0, me);
@@ -1543,7 +1507,6 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
break;
case TCG_TYPE_I64:
if (ret < TCG_REG_V0) {
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_mem_long(s, LD, LDX, ret, base, offset);
break;
}
@@ -1598,7 +1561,6 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
break;
case TCG_TYPE_I64:
if (arg < TCG_REG_V0) {
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64);
tcg_out_mem_long(s, STD, STDX, arg, base, offset);
break;
}
@@ -1641,7 +1603,7 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
static void tcg_out_test(TCGContext *s, TCGReg dest, TCGReg arg1, TCGArg arg2,
bool const_arg2, TCGType type, bool rc)
{
- int mb, me;
+ int mb, me, sh;
if (!const_arg2) {
tcg_out32(s, AND | SAB(arg1, dest, arg2) | rc);
@@ -1664,12 +1626,10 @@ static void tcg_out_test(TCGContext *s, TCGReg dest, TCGReg arg1, TCGArg arg2,
tcg_out_rlw_rc(s, RLWINM, dest, arg1, 0, mb, me, rc);
return;
}
- if (TCG_TARGET_REG_BITS == 64) {
- int sh = clz64(arg2);
- if (mask64_operand(arg2 << sh, &mb, &me)) {
- tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc);
- return;
- }
+ sh = clz64(arg2);
+ if (mask64_operand(arg2 << sh, &mb, &me)) {
+ tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc);
+ return;
}
/* Constraints should satisfy this. */
g_assert_not_reached();
@@ -1680,8 +1640,6 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
{
uint32_t op;
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
-
/*
* Simplify the comparisons below wrt CMPI.
* All of the tests are 16-bit, so a 32-bit sign extend always works.
@@ -1747,7 +1705,7 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
TCGReg dst, TCGReg src, bool neg)
{
- if (neg && (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I64)) {
+ if (neg && type == TCG_TYPE_I64) {
/*
* X != 0 implies X + -1 generates a carry.
* RT = (~X + X) + CA
@@ -1774,7 +1732,7 @@ static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
static void tcg_out_setcond_ne0(TCGContext *s, TCGType type,
TCGReg dst, TCGReg src, bool neg)
{
- if (!neg && (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I64)) {
+ if (!neg && type == TCG_TYPE_I64) {
/*
* X != 0 implies X + -1 generates a carry. Extra addition
* trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C.
@@ -1814,8 +1772,6 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
int sh;
bool inv;
- tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
-
/* Ignore high bits of a potential constant arg2. */
if (type == TCG_TYPE_I32) {
arg2 = (uint32_t)arg2;
@@ -2117,109 +2073,6 @@ static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc,
}
}
-static void tcg_out_cmp2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
- TCGArg bl, bool blconst, TCGArg bh, bool bhconst)
-{
- static const struct { uint8_t bit1, bit2; } bits[] = {
- [TCG_COND_LT ] = { CR_LT, CR_LT },
- [TCG_COND_LE ] = { CR_LT, CR_GT },
- [TCG_COND_GT ] = { CR_GT, CR_GT },
- [TCG_COND_GE ] = { CR_GT, CR_LT },
- [TCG_COND_LTU] = { CR_LT, CR_LT },
- [TCG_COND_LEU] = { CR_LT, CR_GT },
- [TCG_COND_GTU] = { CR_GT, CR_GT },
- [TCG_COND_GEU] = { CR_GT, CR_LT },
- };
-
- TCGCond cond2;
- int op, bit1, bit2;
-
- switch (cond) {
- case TCG_COND_EQ:
- op = CRAND;
- goto do_equality;
- case TCG_COND_NE:
- op = CRNAND;
- do_equality:
- tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
- tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
- tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
- break;
-
- case TCG_COND_TSTEQ:
- case TCG_COND_TSTNE:
- if (blconst) {
- tcg_out_andi32(s, TCG_REG_R0, al, bl);
- } else {
- tcg_out32(s, AND | SAB(al, TCG_REG_R0, bl));
- }
- if (bhconst) {
- tcg_out_andi32(s, TCG_REG_TMP1, ah, bh);
- } else {
- tcg_out32(s, AND | SAB(ah, TCG_REG_TMP1, bh));
- }
- tcg_out32(s, OR | SAB(TCG_REG_R0, TCG_REG_R0, TCG_REG_TMP1) | 1);
- break;
-
- case TCG_COND_LT:
- case TCG_COND_LE:
- case TCG_COND_GT:
- case TCG_COND_GE:
- case TCG_COND_LTU:
- case TCG_COND_LEU:
- case TCG_COND_GTU:
- case TCG_COND_GEU:
- bit1 = bits[cond].bit1;
- bit2 = bits[cond].bit2;
- op = (bit1 != bit2 ? CRANDC : CRAND);
- cond2 = tcg_unsigned_cond(cond);
-
- tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
- tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
- tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
- tcg_out32(s, CROR | BT(0, CR_EQ) | BA(6, bit1) | BB(0, CR_EQ));
- break;
-
- default:
- g_assert_not_reached();
- }
-}
-
-static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret,
- TCGReg al, TCGReg ah,
- TCGArg bl, bool const_bl,
- TCGArg bh, bool const_bh)
-{
- tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh);
- tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(0));
- tcg_out_rlw(s, RLWINM, ret, TCG_REG_R0, CR_EQ + 0*4 + 1, 31, 31);
-}
-
-#if TCG_TARGET_REG_BITS != 32
-__attribute__((unused))
-#endif
-static const TCGOutOpSetcond2 outop_setcond2 = {
- .base.static_constraint = C_O1_I4(r, r, r, rU, rC),
- .out = tgen_setcond2,
-};
-
-static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah,
- TCGArg bl, bool const_bl,
- TCGArg bh, bool const_bh, TCGLabel *l)
-{
- assert(TCG_TARGET_REG_BITS == 32);
- tcg_out_cmp2(s, cond, al, ah, bl, const_bl, bh, const_bh);
- tcg_out_bc_lab(s, TCG_COND_EQ, l);
-}
-
-#if TCG_TARGET_REG_BITS != 32
-__attribute__((unused))
-#endif
-static const TCGOutOpBrcond2 outop_brcond2 = {
- .base.static_constraint = C_O0_I4(r, r, rU, rC),
- .out = tgen_brcond2,
-};
-
static void tcg_out_mb(TCGContext *s, unsigned a0)
{
uint32_t insn;
@@ -2438,13 +2291,8 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off);
/* Extract the page index, shifted into place for tlb index. */
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_shri32(s, TCG_REG_R0, addr,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- } else {
- tcg_out_shri64(s, TCG_REG_R0, addr,
- TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
- }
+ tcg_out_shri64(s, TCG_REG_R0, addr,
+ TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0));
/*
@@ -2453,8 +2301,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
* We will ignore the high bits with tcg_out_cmp(..., addr_type).
*/
if (cmp_off == 0) {
- tcg_out32(s, (TCG_TARGET_REG_BITS == 64 ? LDUX : LWZUX)
- | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
+ tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2));
} else {
tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2));
tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off);
@@ -2464,51 +2311,36 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
* Load the TLB addend for use on the fast path.
* Do this asap to minimize any load use delay.
*/
- if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) {
- tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
- offsetof(CPUTLBEntry, addend));
- }
+ tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1,
+ offsetof(CPUTLBEntry, addend));
/* Clear the non-page, non-alignment bits from the address in R0. */
- if (TCG_TARGET_REG_BITS == 32) {
- /*
- * We don't support unaligned accesses on 32-bits.
- * Preserve the bottom bits and thus trigger a comparison
- * failure on unaligned accesses.
- */
- if (a_bits < s_bits) {
- a_bits = s_bits;
- }
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr, 0,
+ TCGReg t = addr;
+
+ /*
+ * If the access is unaligned, we need to make sure we fail if we
+ * cross a page boundary. The trick is to add the access size-1
+ * to the address before masking the low bits. That will make the
+ * address overflow to the next page if we cross a page boundary,
+ * which will then force a mismatch of the TLB compare.
+ */
+ if (a_bits < s_bits) {
+ unsigned a_mask = (1 << a_bits) - 1;
+ unsigned s_mask = (1 << s_bits) - 1;
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
+ t = TCG_REG_R0;
+ }
+
+ /* Mask the address for the requested alignment. */
+ if (addr_type == TCG_TYPE_I32) {
+ tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
(32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
+ } else if (a_bits == 0) {
+ tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
} else {
- TCGReg t = addr;
-
- /*
- * If the access is unaligned, we need to make sure we fail if we
- * cross a page boundary. The trick is to add the access size-1
- * to the address before masking the low bits. That will make the
- * address overflow to the next page if we cross a page boundary,
- * which will then force a mismatch of the TLB compare.
- */
- if (a_bits < s_bits) {
- unsigned a_mask = (1 << a_bits) - 1;
- unsigned s_mask = (1 << s_bits) - 1;
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask));
- t = TCG_REG_R0;
- }
-
- /* Mask the address for the requested alignment. */
- if (addr_type == TCG_TYPE_I32) {
- tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0,
- (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
- } else if (a_bits == 0) {
- tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS);
- } else {
- tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
- 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
- tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
- }
+ tcg_out_rld(s, RLDICL, TCG_REG_R0, t,
+ 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits);
+ tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
}
/* Full comparison into cr0. */
@@ -2537,7 +2369,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
h->base = guest_base ? TCG_GUEST_BASE_REG : 0;
}
- if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) {
+ if (addr_type == TCG_TYPE_I32) {
/* Zero-extend the guest address for use in the host address. */
tcg_out_ext32u(s, TCG_REG_TMP2, addr);
h->index = TCG_REG_TMP2;
@@ -2554,40 +2386,22 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi,
MemOp opc = get_memop(oi);
TCGLabelQemuLdst *ldst;
HostAddress h;
+ uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
ldst = prepare_host_addr(s, &h, addr, oi, true);
- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
- if (opc & MO_BSWAP) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
- tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
- tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0));
- } else if (h.base != 0) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
- tcg_out32(s, LWZX | TAB(datahi, h.base, h.index));
- tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0));
- } else if (h.index == datahi) {
- tcg_out32(s, LWZ | TAI(datalo, h.index, 4));
- tcg_out32(s, LWZ | TAI(datahi, h.index, 0));
- } else {
- tcg_out32(s, LWZ | TAI(datahi, h.index, 0));
- tcg_out32(s, LWZ | TAI(datalo, h.index, 4));
- }
+ if (!have_isa_2_06 && insn == LDBRX) {
+ tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
+ tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
+ tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0));
+ tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
+ } else if (insn) {
+ tcg_out32(s, insn | TAB(datalo, h.base, h.index));
} else {
- uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
- if (!have_isa_2_06 && insn == LDBRX) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
- tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index));
- tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0));
- tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
- } else if (insn) {
- tcg_out32(s, insn | TAB(datalo, h.base, h.index));
- } else {
- insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
- tcg_out32(s, insn | TAB(datalo, h.base, h.index));
- tcg_out_movext(s, TCG_TYPE_REG, datalo,
- TCG_TYPE_REG, opc & MO_SSIZE, datalo);
- }
+ insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
+ tcg_out32(s, insn | TAB(datalo, h.base, h.index));
+ tcg_out_movext(s, TCG_TYPE_REG, datalo,
+ TCG_TYPE_REG, opc & MO_SSIZE, datalo);
}
if (ldst) {
@@ -2604,32 +2418,17 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi,
MemOp opc = get_memop(oi);
TCGLabelQemuLdst *ldst;
HostAddress h;
+ uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
ldst = prepare_host_addr(s, &h, addr, oi, false);
- if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
- if (opc & MO_BSWAP) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
- tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
- tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0));
- } else if (h.base != 0) {
- tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4));
- tcg_out32(s, STWX | SAB(datahi, h.base, h.index));
- tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0));
- } else {
- tcg_out32(s, STW | TAI(datahi, h.index, 0));
- tcg_out32(s, STW | TAI(datalo, h.index, 4));
- }
+ if (!have_isa_2_06 && insn == STDBRX) {
+ tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
+ tcg_out32(s, ADDI | TAI(TCG_REG_TMP2, h.index, 4));
+ tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
+ tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP2));
} else {
- uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
- if (!have_isa_2_06 && insn == STDBRX) {
- tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index));
- tcg_out32(s, ADDI | TAI(TCG_REG_TMP2, h.index, 4));
- tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
- tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP2));
- } else {
- tcg_out32(s, insn | SAB(datalo, h.base, h.index));
- }
+ tcg_out32(s, insn | SAB(datalo, h.base, h.index));
}
if (ldst) {
@@ -2709,16 +2508,11 @@ static const TCGOutOpQemuLdSt outop_qemu_ld = {
static void tgen_qemu_ld2(TCGContext *s, TCGType type, TCGReg datalo,
TCGReg datahi, TCGReg addr, MemOpIdx oi)
{
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_qemu_ld(s, datalo, datahi, addr, oi, type);
- } else {
- tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, true);
- }
+ tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, true);
}
static const TCGOutOpQemuLdSt2 outop_qemu_ld2 = {
- .base.static_constraint =
- TCG_TARGET_REG_BITS == 64 ? C_N1O1_I1(o, m, r) : C_O2_I1(r, r, r),
+ .base.static_constraint = C_N1O1_I1(o, m, r),
.out = tgen_qemu_ld2,
};
@@ -2736,16 +2530,11 @@ static const TCGOutOpQemuLdSt outop_qemu_st = {
static void tgen_qemu_st2(TCGContext *s, TCGType type, TCGReg datalo,
TCGReg datahi, TCGReg addr, MemOpIdx oi)
{
- if (TCG_TARGET_REG_BITS == 32) {
- tcg_out_qemu_st(s, datalo, datahi, addr, oi, type);
- } else {
- tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, false);
- }
+ tcg_out_qemu_ldst_i128(s, datalo, datahi, addr, oi, false);
}
static const TCGOutOpQemuLdSt2 outop_qemu_st2 = {
- .base.static_constraint =
- TCG_TARGET_REG_BITS == 64 ? C_O0_I3(o, m, r) : C_O0_I3(r, r, r),
+ .base.static_constraint = C_O0_I3(o, m, r),
.out = tgen_qemu_st2,
};
@@ -2767,16 +2556,11 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
#elif defined(_CALL_DARWIN)
# define LINK_AREA_SIZE (6 * SZR)
# define LR_OFFSET (2 * SZR)
-#elif TCG_TARGET_REG_BITS == 64
+#else
# if defined(_CALL_ELF) && _CALL_ELF == 2
# define LINK_AREA_SIZE (4 * SZR)
# define LR_OFFSET (1 * SZR)
# endif
-#else /* TCG_TARGET_REG_BITS == 32 */
-# if defined(_CALL_SYSV)
-# define LINK_AREA_SIZE (2 * SZR)
-# define LR_OFFSET (1 * SZR)
-# endif
#endif
#ifndef LR_OFFSET
# error "Unhandled abi"
@@ -3107,7 +2891,6 @@ static void tgen_eqv(TCGContext *s, TCGType type,
tcg_out32(s, EQV | SAB(a1, a0, a2));
}
-#if TCG_TARGET_REG_BITS == 64
static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1)
{
tcg_out_shri64(s, a0, a1, 32);
@@ -3117,7 +2900,6 @@ static const TCGOutOpUnary outop_extrh_i64_i32 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_extrh_i64_i32,
};
-#endif
static void tgen_divs(TCGContext *s, TCGType type,
TCGReg a0, TCGReg a1, TCGReg a2)
@@ -3596,7 +3378,6 @@ static const TCGOutOpBswap outop_bswap32 = {
.out_rr = tgen_bswap32,
};
-#if TCG_TARGET_REG_BITS == 64
static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg dst, TCGReg src)
{
TCGReg t0 = dst == src ? TCG_REG_R0 : dst;
@@ -3639,7 +3420,6 @@ static const TCGOutOpUnary outop_bswap64 = {
.base.static_constraint = C_O1_I1(r, r),
.out_rr = tgen_bswap64,
};
-#endif /* TCG_TARGET_REG_BITS == 64 */
static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1)
{
@@ -3776,7 +3556,6 @@ static const TCGOutOpLoad outop_ld16s = {
.out = tgen_ld16s,
};
-#if TCG_TARGET_REG_BITS == 64
static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest,
TCGReg base, ptrdiff_t offset)
{
@@ -3798,7 +3577,6 @@ static const TCGOutOpLoad outop_ld32s = {
.base.static_constraint = C_O1_I1(r, r),
.out = tgen_ld32s,
};
-#endif
static void tgen_st8(TCGContext *s, TCGType type, TCGReg data,
TCGReg base, ptrdiff_t offset)
@@ -4278,14 +4056,6 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
tcg_out_bitsel_vec(s, a0, a1, a2, args[3]);
return;
- case INDEX_op_dup2_vec:
- assert(TCG_TARGET_REG_BITS == 32);
- /* With inputs a1 = xLxx, a2 = xHxx */
- tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */
- tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */
- tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */
- return;
-
case INDEX_op_ppc_mrgh_vec:
insn = mrgh_op[vece];
break;
@@ -4465,7 +4235,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
case INDEX_op_ppc_muleu_vec:
case INDEX_op_ppc_mulou_vec:
case INDEX_op_ppc_pkum_vec:
- case INDEX_op_dup2_vec:
return C_O1_I2(v, v, v);
case INDEX_op_not_vec:
@@ -4543,9 +4312,7 @@ static void tcg_target_init(TCGContext *s)
#if defined(_CALL_SYSV)
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
#endif
-#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
-#endif
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1);
@@ -4566,11 +4333,7 @@ typedef struct {
/* We're expecting a 2 byte uleb128 encoded value. */
QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
-#if TCG_TARGET_REG_BITS == 64
-# define ELF_HOST_MACHINE EM_PPC64
-#else
-# define ELF_HOST_MACHINE EM_PPC
-#endif
+#define ELF_HOST_MACHINE EM_PPC64
static DebugFrame debug_frame = {
.cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
--
2.43.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PULL 0/9] tcg patch queue
2025-10-19 18:28 [PULL 0/9] tcg patch queue Richard Henderson
` (8 preceding siblings ...)
2025-10-19 18:28 ` [PULL 9/9] tcg/ppc: Remove support for 32-bit hosts Richard Henderson
@ 2025-10-19 19:35 ` Richard Henderson
9 siblings, 0 replies; 11+ messages in thread
From: Richard Henderson @ 2025-10-19 19:35 UTC (permalink / raw)
To: qemu-devel
On 10/19/25 11:28, Richard Henderson wrote:
> The following changes since commit 18f6f30b0089b470f3e737637a86dfb81ebd6eae:
>
> Merge tag 'pull-request-2025-10-16' ofhttps://gitlab.com/thuth/qemu into staging (2025-10-16 12:27:12 -0700)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20251019
>
> for you to fetch changes up to 5c1ec5a1ee0958068a532ac1e06cc6cee0c75ba3:
>
> tcg/ppc: Remove support for 32-bit hosts (2025-10-19 11:24:34 -0700)
>
> ----------------------------------------------------------------
> tcg: Remove support for 32-bit mips/ppc hosts
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
r~
^ permalink raw reply [flat|nested] 11+ messages in thread