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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-475c4369b33sm9444135e9.14.2025.10.21.13.57.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 21 Oct 2025 13:57:43 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Anton Johansson , Peter Maydell , Luc Michel , Zhao Liu , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v7 00/19] single-binary: Make hw/arm/ common Date: Tue, 21 Oct 2025 22:57:21 +0200 Message-ID: <20251021205741.57109-1-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Series fully reviewed. Since v6: - Addressed Jan comment - Removed aspeed/raspi meson patches Since v5: - Rebased - Use Zoltan's patch - Filter QMP list - Addressed Richard & Pierrick comments - qtest/device-introspect-test failing Since v4: - Add DEFINE_MACHINE_WITH_INTERFACES (Zoltan) - Use GPtrArray for get_valid_cpu_type (Richard) - Define InterfaceInfo[] arrays (Richard) - Collect R-b tags Since v3: - QAPI structure renamed as QemuTargetInfo - MachineClass::get_valid_cpu_types() runtime - target_aarch64() checking SysEmuTarget value - Remove CONFIG_TCG #ifdef'ry in hw/arm/ Since v2: - More comments from Pierrick addressed - Use GList to register valid CPUs list - Remove all TARGET_AARCH64 uses in hw/arm/ Since v1: - Dropped unrelated / irrelevant patches - Addressed Pierrick comments - Added R-b tag - Only considering machines, not CPUs. Based-on: <20251021204700.56072-1-philmd@linaro.org> Available here, based on hw-misc: https://gitlab.com/philmd/qemu/-/tags/single-binary-hw-arm-rfc-v7 Philippe Mathieu-Daudé (19): hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine hw/arm: Add DEFINE_MACHINE_ARM() / DEFINE_MACHINE_AARCH64() macros hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries meson: Prepare to accept per-binary TargetInfo structure implementation config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) hw/arm/virt: Register valid CPU types dynamically hw/arm/virt: Check accelerator availability at runtime qemu/target_info: Add target_arm() helper qemu/target_info: Add target_aarch64() helper qemu/target_info: Add target_base_arm() helper hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() hw/arm/virt: Get default CPU type at runtime hw/arm/sbsa-ref: Include missing 'cpu.h' header hw/arm/sbsa-ref: Build only once hw/arm/virt-acpi-build: Include missing 'cpu.h' header hw/arm/virt-acpi-build: Build only once hw/arm/virt: Build only once hw/arm/meson: Move Xen files to arm_common_ss[] MAINTAINERS | 1 + meson.build | 10 ++++- include/hw/arm/machines-qom.h | 46 +++++++++++++++++++ include/qemu/target-info.h | 21 +++++++++ configs/targets/aarch64-softmmu.c | 26 +++++++++++ configs/targets/arm-softmmu.c | 26 +++++++++++ hw/arm/aspeed.c | 27 ++++++++++- hw/arm/aspeed_ast27x0-fc.c | 2 + hw/arm/b-l475e-iot01a.c | 2 + hw/arm/bananapi_m2u.c | 3 +- hw/arm/collie.c | 2 + hw/arm/cubieboard.c | 3 +- hw/arm/digic_boards.c | 3 +- hw/arm/exynos4_boards.c | 3 ++ hw/arm/fby35.c | 2 + hw/arm/highbank.c | 3 ++ hw/arm/imx25_pdk.c | 3 +- hw/arm/imx8mp-evk.c | 4 +- hw/arm/integratorcp.c | 3 +- hw/arm/kzm.c | 3 +- hw/arm/mcimx6ul-evk.c | 4 +- hw/arm/mcimx7d-sabre.c | 4 +- hw/arm/microbit.c | 2 + hw/arm/mps2-tz.c | 5 +++ hw/arm/mps2.c | 5 +++ hw/arm/mps3r.c | 2 + hw/arm/msf2-som.c | 3 +- hw/arm/musca.c | 3 ++ hw/arm/musicpal.c | 3 +- hw/arm/netduino2.c | 3 +- hw/arm/netduinoplus2.c | 3 +- hw/arm/npcm7xx_boards.c | 6 +++ hw/arm/npcm8xx_boards.c | 2 + hw/arm/olimex-stm32-h405.c | 3 +- hw/arm/omap_sx1.c | 3 ++ hw/arm/orangepi.c | 3 +- hw/arm/raspi.c | 6 +++ hw/arm/raspi4b.c | 2 + hw/arm/realview.c | 5 +++ hw/arm/sabrelite.c | 3 +- hw/arm/sbsa-ref.c | 3 ++ hw/arm/stellaris.c | 3 ++ hw/arm/stm32vldiscovery.c | 3 +- hw/arm/versatilepb.c | 3 ++ hw/arm/vexpress.c | 3 ++ hw/arm/virt-acpi-build.c | 1 + hw/arm/virt.c | 74 ++++++++++++++++++------------- hw/arm/xilinx_zynq.c | 2 + hw/arm/xlnx-versal-virt.c | 3 ++ hw/arm/xlnx-zcu102.c | 2 + hw/core/null-machine.c | 6 ++- target-info-qom.c | 24 ++++++++++ target-info.c | 21 +++++++++ target/arm/machine.c | 18 ++++++++ configs/targets/meson.build | 5 +++ hw/arm/meson.build | 8 ++-- 56 files changed, 386 insertions(+), 56 deletions(-) create mode 100644 include/hw/arm/machines-qom.h create mode 100644 configs/targets/aarch64-softmmu.c create mode 100644 configs/targets/arm-softmmu.c create mode 100644 target-info-qom.c create mode 100644 configs/targets/meson.build -- 2.51.0