* [PULL 01/16] hw/arm/aspeed_ast27x0-ssp: Add SDRAM region and fix naming and size to 512MB
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 02/16] hw/arm/aspeed_ast27x0-tsp: " Cédric Le Goater
` (15 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Previously, the SSP memory was incorrectly modeled as "SRAM" with
a 32 MB size. This change introduces a new sdram field in
AspeedCoprocessorState and updates the realization logic accordingly.
Rename from SRAM to SDRAM and correct size from 32MB to 512MB to match
hardware.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-2-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_coprocessor.h | 1 +
hw/arm/aspeed_ast27x0-ssp.c | 20 ++++++++++----------
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index d77655d65911..0c7168a89c15 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -16,6 +16,7 @@ struct AspeedCoprocessorState {
DeviceState parent;
MemoryRegion *memory;
+ MemoryRegion sdram;
MemoryRegion sram;
Clock *sysclk;
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 936c7c72e8f7..9f3a1933a066 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -16,10 +16,10 @@
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/aspeed_coprocessor.h"
-#define AST2700_SSP_RAM_SIZE (32 * MiB)
+#define AST2700_SSP_SDRAM_SIZE (512 * MiB)
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
- [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_SDRAM] = 0x00000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -165,7 +165,7 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
- g_autofree char *sram_name = NULL;
+ g_autofree char *sdram_name = NULL;
int uart;
int i;
@@ -184,16 +184,16 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
OBJECT(s->memory), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
- sram_name = g_strdup_printf("aspeed.dram.%d",
- CPU(a->armv7m.cpu)->cpu_index);
-
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
- AST2700_SSP_RAM_SIZE, errp)) {
+ /* SDRAM */
+ sdram_name = g_strdup_printf("aspeed.sdram.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
+ if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name,
+ AST2700_SSP_SDRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM],
- &s->sram);
+ sc->memmap[ASPEED_DEV_SDRAM],
+ &s->sdram);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 02/16] hw/arm/aspeed_ast27x0-tsp: Add SDRAM region and fix naming and size to 512MB
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
2025-10-22 12:29 ` [PULL 01/16] hw/arm/aspeed_ast27x0-ssp: Add SDRAM region and fix naming and size to 512MB Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 03/16] hw/arm/ast27x0: Add SRAM link and alias mapping for SSP coprocessor Cédric Le Goater
` (14 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Previously, the TSP memory was incorrectly modeled as "SRAM" with
a 32 MB size. Rename from SRAM to SDRAM and correct size from 32MB
to 512MB to match hardware.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-3-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-tsp.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 9318f8c86c51..caeb3392a8e6 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -16,10 +16,10 @@
#include "hw/arm/aspeed_soc.h"
#include "hw/arm/aspeed_coprocessor.h"
-#define AST2700_TSP_RAM_SIZE (32 * MiB)
+#define AST2700_TSP_SDRAM_SIZE (512 * MiB)
static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
- [ASPEED_DEV_SRAM] = 0x00000000,
+ [ASPEED_DEV_SDRAM] = 0x00000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -165,7 +165,7 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(dev_soc);
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
- g_autofree char *sram_name = NULL;
+ g_autofree char *sdram_name = NULL;
int uart;
int i;
@@ -184,16 +184,16 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
OBJECT(s->memory), &error_abort);
sysbus_realize(SYS_BUS_DEVICE(&a->armv7m), &error_abort);
- sram_name = g_strdup_printf("aspeed.dram.%d",
- CPU(a->armv7m.cpu)->cpu_index);
-
- if (!memory_region_init_ram(&s->sram, OBJECT(s), sram_name,
- AST2700_TSP_RAM_SIZE, errp)) {
+ /* SDRAM */
+ sdram_name = g_strdup_printf("aspeed.sdram.%d",
+ CPU(a->armv7m.cpu)->cpu_index);
+ if (!memory_region_init_ram(&s->sdram, OBJECT(s), sdram_name,
+ AST2700_TSP_SDRAM_SIZE, errp)) {
return;
}
memory_region_add_subregion(s->memory,
- sc->memmap[ASPEED_DEV_SRAM],
- &s->sram);
+ sc->memmap[ASPEED_DEV_SDRAM],
+ &s->sdram);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 03/16] hw/arm/ast27x0: Add SRAM link and alias mapping for SSP coprocessor
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
2025-10-22 12:29 ` [PULL 01/16] hw/arm/aspeed_ast27x0-ssp: Add SDRAM region and fix naming and size to 512MB Cédric Le Goater
2025-10-22 12:29 ` [PULL 02/16] hw/arm/aspeed_ast27x0-tsp: " Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 04/16] hw/arm/ast27x0: Add SRAM link and alias mapping for TSP coprocessor Cédric Le Goater
` (13 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for
the PSP (CA35) processor. The SSP coprocessor shares this same SRAM but
accesses it through a different address window at 0x70000000–0x7001FFFF.
To model this shared-memory behavior in QEMU, this commit introduces a
linked SRAM property and alias mapping between the PSP and SSP subsystems.
Changes include:
- Add a "MemoryRegion *sram" link and "MemoryRegion sram_alias" to
AspeedCoprocessorState.
- Register the new "sram" property in aspeed_coprocessor_common.c.
- In aspeed_ast27x0-fc.c, connect the SSP coprocessor’s "sram" link to
the PSP’s SRAM region.
- In aspeed_ast27x0-ssp.c, create an alias mapping for SRAM at
0x70000000 – 0x7001FFFF in the SSP’s memory map.
This ensures that the SSP can correctly access the shared SRAM contents
through its own address space while maintaining a consistent physical
backing region. It also guarantees that the SRAM is realized before the
SSP device, ensuring successful alias setup.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-4-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_coprocessor.h | 3 ++-
hw/arm/aspeed_ast27x0-fc.c | 4 ++++
hw/arm/aspeed_ast27x0-ssp.c | 7 +++++++
hw/arm/aspeed_coprocessor_common.c | 2 ++
4 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index 0c7168a89c15..d9a5f517d7c7 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -17,7 +17,8 @@ struct AspeedCoprocessorState {
MemoryRegion *memory;
MemoryRegion sdram;
- MemoryRegion sram;
+ MemoryRegion *sram;
+ MemoryRegion sram_alias;
Clock *sysclk;
AspeedSCUState scu;
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index a61ecff3909b..25e668a648fa 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -118,6 +118,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
AspeedCoprocessorState *soc;
AspeedCoprocessorClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
+ AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
+
s->ssp_sysclk = clock_new(OBJECT(s), "SSP_SYSCLK");
clock_set_hz(s->ssp_sysclk, 200000000ULL);
@@ -134,6 +136,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
sc = ASPEED_COPROCESSOR_GET_CLASS(soc);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base,
sc->uarts_num, serial_hd(1));
+ object_property_set_link(OBJECT(&s->ssp), "sram",
+ OBJECT(&psp->sram), &error_abort);
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 9f3a1933a066..66c4ef6d1b74 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -20,6 +20,7 @@
static const hwaddr aspeed_soc_ast27x0ssp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -195,6 +196,12 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SDRAM],
&s->sdram);
+ /* SRAM */
+ memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
+ s->sram, 0, memory_region_size(s->sram));
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ &s->sram_alias);
+
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor_common.c
index 8a94b44f07f2..8322ad5eb544 100644
--- a/hw/arm/aspeed_coprocessor_common.c
+++ b/hw/arm/aspeed_coprocessor_common.c
@@ -25,6 +25,8 @@ static void aspeed_coprocessor_realize(DeviceState *dev, Error **errp)
static const Property aspeed_coprocessor_properties[] = {
DEFINE_PROP_LINK("memory", AspeedCoprocessorState, memory,
TYPE_MEMORY_REGION, MemoryRegion *),
+ DEFINE_PROP_LINK("sram", AspeedCoprocessorState, sram, TYPE_MEMORY_REGION,
+ MemoryRegion *),
};
static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 04/16] hw/arm/ast27x0: Add SRAM link and alias mapping for TSP coprocessor
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (2 preceding siblings ...)
2025-10-22 12:29 ` [PULL 03/16] hw/arm/ast27x0: Add SRAM link and alias mapping for SSP coprocessor Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 05/16] hw/arm/ast27x0: Share single SCU instance across PSP, SSP, and TSP Cédric Le Goater
` (12 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for
the PSP (CA35) processor. The TSP coprocessor shares this same SRAM but
accesses it through a different address window at 0x70000000–0x7001FFFF.
To model this shared-memory behavior in QEMU, this commit introduces a
linked SRAM property and alias mapping between the PSP and TSP subsystems.
Changes include:
- Add the SRAM alias mapping at 0x70000000 in aspeed_ast27x0-tsp.c.
- In aspeed_ast27x0-fc.c, connect the TSP coprocessor’s "sram" link to
the PSP’s SRAM region.
- Ensure the alias region is initialized during TSP SoC realization so
the TSP can correctly access shared SRAM through its own address space.
This ensures that the TSP and PSP share the same physical SRAM backing.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-5-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-fc.c | 4 ++++
hw/arm/aspeed_ast27x0-tsp.c | 7 +++++++
2 files changed, 11 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 25e668a648fa..dfac7d1e17b8 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -150,6 +150,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
AspeedCoprocessorState *soc;
AspeedCoprocessorClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
+ AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
+
s->tsp_sysclk = clock_new(OBJECT(s), "TSP_SYSCLK");
clock_set_hz(s->tsp_sysclk, 200000000ULL);
@@ -166,6 +168,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
sc = ASPEED_COPROCESSOR_GET_CLASS(soc);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
sc->uarts_num, serial_hd(2));
+ object_property_set_link(OBJECT(&s->tsp), "sram",
+ OBJECT(&psp->sram), &error_abort);
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index caeb3392a8e6..56b68adf541b 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -20,6 +20,7 @@
static const hwaddr aspeed_soc_ast27x0tsp_memmap[] = {
[ASPEED_DEV_SDRAM] = 0x00000000,
+ [ASPEED_DEV_SRAM] = 0x70000000,
[ASPEED_DEV_INTC] = 0x72100000,
[ASPEED_DEV_SCU] = 0x72C02000,
[ASPEED_DEV_SCUIO] = 0x74C02000,
@@ -195,6 +196,12 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
sc->memmap[ASPEED_DEV_SDRAM],
&s->sdram);
+ /* SRAM */
+ memory_region_init_alias(&s->sram_alias, OBJECT(s), "sram.alias",
+ s->sram, 0, memory_region_size(s->sram));
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM],
+ &s->sram_alias);
+
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
return;
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 05/16] hw/arm/ast27x0: Share single SCU instance across PSP, SSP, and TSP
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (3 preceding siblings ...)
2025-10-22 12:29 ` [PULL 04/16] hw/arm/ast27x0: Add SRAM link and alias mapping for TSP coprocessor Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 06/16] hw/arm/ast27x0: Share single UART set " Cédric Le Goater
` (11 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
AST2700 has a single SCU hardware block, memory-mapped at
0x12C02000–0x12C03FFF from the perspective of the main CA35 processor (PSP).
The SSP and TSP coprocessors access this same SCU block at different
addresses: 0x72C02000–0x72C03FFF.
Previously, each subsystem (PSP, SSP, and TSP) instantiated its own SCU
device, resulting in three independent SCU instances in the QEMU model.
In real hardware, however, only a single SCU exists and is shared among
all processors.
This commit reworks the SCU model to correctly reflect the hardware
behavior by allowing SSP and TSP to reference the PSP’s SCU instance.
The following changes are introduced:
- Add a scu property to AspeedCoprocessorState for linking the
coprocessor to the PSP’s SCU instance.
- Replace per-coprocessor SCU instantiation with a shared SCU link.
- Add "MemoryRegion scu_alias" to model address remapping for SSP and TSP.
- Create SCU alias regions in both SSP and TSP coprocessors and map
them at 0x72C02000 to mirror the PSP’s SCU registers.
- Ensure the SCU device in PSP is realized before SSP/TSP alias setup.
With this change, PSP, SSP, and TSP now share a consistent SCU state,
matching the single-SCU hardware design of AST2700.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-6-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_coprocessor.h | 4 ++--
hw/arm/aspeed_ast27x0-fc.c | 4 ++++
hw/arm/aspeed_ast27x0-ssp.c | 13 +++++--------
hw/arm/aspeed_ast27x0-tsp.c | 13 +++++--------
hw/arm/aspeed_coprocessor_common.c | 2 ++
5 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index d9a5f517d7c7..c1f2c549c323 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -19,9 +19,10 @@ struct AspeedCoprocessorState {
MemoryRegion sdram;
MemoryRegion *sram;
MemoryRegion sram_alias;
+ MemoryRegion scu_alias;
Clock *sysclk;
- AspeedSCUState scu;
+ AspeedSCUState *scu;
AspeedSCUState scuio;
AspeedTimerCtrlState timerctrl;
SerialMM uart[ASPEED_UARTS_NUM];
@@ -36,7 +37,6 @@ struct AspeedCoprocessorClass {
/** valid_cpu_types: NULL terminated array of a single CPU type. */
const char * const *valid_cpu_types;
- uint32_t silicon_rev;
const hwaddr *memmap;
const int *irqmap;
int uarts_base;
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index dfac7d1e17b8..ba43a4620760 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -138,6 +138,8 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(1));
object_property_set_link(OBJECT(&s->ssp), "sram",
OBJECT(&psp->sram), &error_abort);
+ object_property_set_link(OBJECT(&s->ssp), "scu",
+ OBJECT(&psp->scu), &error_abort);
if (!qdev_realize(DEVICE(&s->ssp), NULL, errp)) {
return false;
}
@@ -170,6 +172,8 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
sc->uarts_num, serial_hd(2));
object_property_set_link(OBJECT(&s->tsp), "sram",
OBJECT(&psp->sram), &error_abort);
+ object_property_set_link(OBJECT(&s->tsp), "scu",
+ OBJECT(&psp->scu), &error_abort);
if (!qdev_realize(DEVICE(&s->tsp), NULL, errp)) {
return false;
}
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 66c4ef6d1b74..577a3379c6c0 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -137,9 +137,7 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
- object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
- qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
for (i = 0; i < sc->uarts_num; i++) {
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
@@ -203,11 +201,11 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
&s->sram_alias);
/* SCU */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
- return;
- }
- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
- sc->memmap[ASPEED_DEV_SCU]);
+ memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias",
+ &s->scu->iomem, 0,
+ memory_region_size(&s->scu->iomem));
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
+ &s->scu_alias);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
@@ -285,7 +283,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
dc->realize = aspeed_soc_ast27x0ssp_realize;
sc->valid_cpu_types = valid_cpu_types;
- sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->uarts_num = 13;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index 56b68adf541b..a7c141678fc2 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -137,9 +137,7 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
- object_initialize_child(obj, "scu", &s->scu, TYPE_ASPEED_2700_SCU);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
- qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->silicon_rev);
for (i = 0; i < sc->uarts_num; i++) {
object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
@@ -203,11 +201,11 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
&s->sram_alias);
/* SCU */
- if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
- return;
- }
- aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0,
- sc->memmap[ASPEED_DEV_SCU]);
+ memory_region_init_alias(&s->scu_alias, OBJECT(s), "scu.alias",
+ &s->scu->iomem, 0,
+ memory_region_size(&s->scu->iomem));
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU],
+ &s->scu_alias);
/* INTC */
if (!sysbus_realize(SYS_BUS_DEVICE(&a->intc[0]), errp)) {
@@ -285,7 +283,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
dc->realize = aspeed_soc_ast27x0tsp_realize;
sc->valid_cpu_types = valid_cpu_types;
- sc->silicon_rev = AST2700_A1_SILICON_REV;
sc->uarts_num = 13;
sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor_common.c
index 8322ad5eb544..14e26bbe234e 100644
--- a/hw/arm/aspeed_coprocessor_common.c
+++ b/hw/arm/aspeed_coprocessor_common.c
@@ -27,6 +27,8 @@ static const Property aspeed_coprocessor_properties[] = {
TYPE_MEMORY_REGION, MemoryRegion *),
DEFINE_PROP_LINK("sram", AspeedCoprocessorState, sram, TYPE_MEMORY_REGION,
MemoryRegion *),
+ DEFINE_PROP_LINK("scu", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU,
+ AspeedSCUState *),
};
static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 06/16] hw/arm/ast27x0: Share single UART set across PSP, SSP, and TSP
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (4 preceding siblings ...)
2025-10-22 12:29 ` [PULL 05/16] hw/arm/ast27x0: Share single SCU instance across PSP, SSP, and TSP Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 07/16] hw/arm/aspeed_ast27x0-fc: Map FMC0 flash contents into CA35 boot ROM Cédric Le Goater
` (10 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
In the original model, each subsystem (PSP, SSP, and TSP) created its own
set of 13 UART devices, resulting in a total of 39 UART instances. However,
on real AST2700 hardware, there is only one set of 13 UARTs shared among
all processors.
This commit reworks the UART handling to correctly model the shared
hardware design. The PSP now creates the full set of 13 UART instances,
while the SSP and TSP link to the corresponding shared UART device
through object properties.
Changes include:
- Add "DEFINE_PROP_LINK("uart", ...)" and "DEFINE_PROP_INT32("uart-dev", ...)"
to allow each coprocessor to reference a specific shared UART instance.
- Modify SSP to link to PSP’s UART4, and TSP to link to PSP’s UART7.
- Introduce "uart_alias" to remap the UART’s MMIO region into the coprocessor’s
memory space.
- Redirect the UART interrupt to the coprocessor’s NVIC, replacing the
default routing to the PSP’s GIC.
With this change, only one set of 13 UART devices is instantiated by the PSP,
while the SSP and TSP reuse them via aliasing and shared interrupt routing,
matching the real AST2700 hardware behavior.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-7-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/hw/arm/aspeed_coprocessor.h | 6 +++---
hw/arm/aspeed_ast27x0-fc.c | 24 ++++++++++++------------
hw/arm/aspeed_ast27x0-ssp.c | 29 ++++++++++++-----------------
hw/arm/aspeed_ast27x0-tsp.c | 29 ++++++++++++-----------------
hw/arm/aspeed_coprocessor_common.c | 3 +++
5 files changed, 42 insertions(+), 49 deletions(-)
diff --git a/include/hw/arm/aspeed_coprocessor.h b/include/hw/arm/aspeed_coprocessor.h
index c1f2c549c323..4a50f688ecdc 100644
--- a/include/hw/arm/aspeed_coprocessor.h
+++ b/include/hw/arm/aspeed_coprocessor.h
@@ -19,13 +19,15 @@ struct AspeedCoprocessorState {
MemoryRegion sdram;
MemoryRegion *sram;
MemoryRegion sram_alias;
+ MemoryRegion uart_alias;
MemoryRegion scu_alias;
Clock *sysclk;
AspeedSCUState *scu;
AspeedSCUState scuio;
AspeedTimerCtrlState timerctrl;
- SerialMM uart[ASPEED_UARTS_NUM];
+ SerialMM *uart;
+ int uart_dev;
};
#define TYPE_ASPEED_COPROCESSOR "aspeed-coprocessor"
@@ -39,8 +41,6 @@ struct AspeedCoprocessorClass {
const char * const *valid_cpu_types;
const hwaddr *memmap;
const int *irqmap;
- int uarts_base;
- int uarts_num;
};
struct Aspeed27x0CoprocessorState {
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index ba43a4620760..99af87dbd7bd 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -93,6 +93,10 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
AST2700FC_HW_STRAP2, &error_abort);
aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART12, sc->uarts_base,
sc->uarts_num, serial_hd(0));
+ aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base,
+ sc->uarts_num, serial_hd(1));
+ aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
+ sc->uarts_num, serial_hd(2));
if (!qdev_realize(DEVICE(&s->ca35), NULL, errp)) {
return false;
}
@@ -115,8 +119,6 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
{
- AspeedCoprocessorState *soc;
- AspeedCoprocessorClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
@@ -132,10 +134,10 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
object_property_set_link(OBJECT(&s->ssp), "memory",
OBJECT(&s->ssp_memory), &error_abort);
- soc = ASPEED_COPROCESSOR(&s->ssp);
- sc = ASPEED_COPROCESSOR_GET_CLASS(soc);
- aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART4, sc->uarts_base,
- sc->uarts_num, serial_hd(1));
+ object_property_set_link(OBJECT(&s->ssp), "uart",
+ OBJECT(&psp->uart[4]), &error_abort);
+ object_property_set_int(OBJECT(&s->ssp), "uart-dev", ASPEED_DEV_UART4,
+ &error_abort);
object_property_set_link(OBJECT(&s->ssp), "sram",
OBJECT(&psp->sram), &error_abort);
object_property_set_link(OBJECT(&s->ssp), "scu",
@@ -149,8 +151,6 @@ static bool ast2700fc_ssp_init(MachineState *machine, Error **errp)
static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
{
- AspeedCoprocessorState *soc;
- AspeedCoprocessorClass *sc;
Ast2700FCState *s = AST2700A1FC(machine);
AspeedSoCState *psp = ASPEED_SOC(&s->ca35);
@@ -166,10 +166,10 @@ static bool ast2700fc_tsp_init(MachineState *machine, Error **errp)
object_property_set_link(OBJECT(&s->tsp), "memory",
OBJECT(&s->tsp_memory), &error_abort);
- soc = ASPEED_COPROCESSOR(&s->tsp);
- sc = ASPEED_COPROCESSOR_GET_CLASS(soc);
- aspeed_soc_uart_set_chr(soc->uart, ASPEED_DEV_UART7, sc->uarts_base,
- sc->uarts_num, serial_hd(2));
+ object_property_set_link(OBJECT(&s->tsp), "uart",
+ OBJECT(&psp->uart[7]), &error_abort);
+ object_property_set_int(OBJECT(&s->tsp), "uart-dev", ASPEED_DEV_UART7,
+ &error_abort);
object_property_set_link(OBJECT(&s->tsp), "sram",
OBJECT(&psp->sram), &error_abort);
object_property_set_link(OBJECT(&s->tsp), "scu",
diff --git a/hw/arm/aspeed_ast27x0-ssp.c b/hw/arm/aspeed_ast27x0-ssp.c
index 577a3379c6c0..d12a9b8459c2 100644
--- a/hw/arm/aspeed_ast27x0-ssp.c
+++ b/hw/arm/aspeed_ast27x0-ssp.c
@@ -133,16 +133,10 @@ static void aspeed_soc_ast27x0ssp_init(Object *obj)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0SSP_COPROCESSOR(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
- AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
- int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
- for (i = 0; i < sc->uarts_num; i++) {
- object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
- }
-
object_initialize_child(obj, "intc0", &a->intc[0],
TYPE_ASPEED_2700SSP_INTC);
object_initialize_child(obj, "intc1", &a->intc[1],
@@ -165,7 +159,6 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sdram_name = NULL;
- int uart;
int i;
if (!clock_has_source(s->sysclk)) {
@@ -244,15 +237,19 @@ static void aspeed_soc_ast27x0ssp_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
+
/* UART */
- for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
- if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
- sc->memmap[uart], errp)) {
- return;
- }
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
- aspeed_soc_ast27x0ssp_get_irq(s, uart));
- }
+ memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias",
+ &s->uart->serial.io, 0,
+ memory_region_size(&s->uart->serial.io));
+ memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev],
+ &s->uart_alias);
+ /*
+ * Redirect the UART interrupt to the NVIC, replacing the default routing
+ * to the PSP's GIC.
+ */
+ sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
+ aspeed_soc_ast27x0ssp_get_irq(s, s->uart_dev));
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
@@ -283,8 +280,6 @@ static void aspeed_soc_ast27x0ssp_class_init(ObjectClass *klass,
dc->realize = aspeed_soc_ast27x0ssp_realize;
sc->valid_cpu_types = valid_cpu_types;
- sc->uarts_num = 13;
- sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast27x0ssp_irqmap;
sc->memmap = aspeed_soc_ast27x0ssp_memmap;
}
diff --git a/hw/arm/aspeed_ast27x0-tsp.c b/hw/arm/aspeed_ast27x0-tsp.c
index a7c141678fc2..5b75e1420639 100644
--- a/hw/arm/aspeed_ast27x0-tsp.c
+++ b/hw/arm/aspeed_ast27x0-tsp.c
@@ -133,16 +133,10 @@ static void aspeed_soc_ast27x0tsp_init(Object *obj)
{
Aspeed27x0CoprocessorState *a = ASPEED27X0TSP_COPROCESSOR(obj);
AspeedCoprocessorState *s = ASPEED_COPROCESSOR(obj);
- AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
- int i;
object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M);
s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
- for (i = 0; i < sc->uarts_num; i++) {
- object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
- }
-
object_initialize_child(obj, "intc0", &a->intc[0],
TYPE_ASPEED_2700TSP_INTC);
object_initialize_child(obj, "intc1", &a->intc[1],
@@ -165,7 +159,6 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
AspeedCoprocessorClass *sc = ASPEED_COPROCESSOR_GET_CLASS(s);
DeviceState *armv7m;
g_autofree char *sdram_name = NULL;
- int uart;
int i;
if (!clock_has_source(s->sysclk)) {
@@ -244,15 +237,19 @@ static void aspeed_soc_ast27x0tsp_realize(DeviceState *dev_soc, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&a->intc[1]), i,
qdev_get_gpio_in(DEVICE(&a->intc[0].orgates[0]), i));
}
+
/* UART */
- for (i = 0, uart = sc->uarts_base; i < sc->uarts_num; i++, uart++) {
- if (!aspeed_soc_uart_realize(s->memory, &s->uart[i],
- sc->memmap[uart], errp)) {
- return;
- }
- sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,
- aspeed_soc_ast27x0tsp_get_irq(s, uart));
- }
+ memory_region_init_alias(&s->uart_alias, OBJECT(s), "uart.alias",
+ &s->uart->serial.io, 0,
+ memory_region_size(&s->uart->serial.io));
+ memory_region_add_subregion(s->memory, sc->memmap[s->uart_dev],
+ &s->uart_alias);
+ /*
+ * Redirect the UART interrupt to the NVIC, replacing the default routing
+ * to the PSP's GIC.
+ */
+ sysbus_connect_irq(SYS_BUS_DEVICE(s->uart), 0,
+ aspeed_soc_ast27x0tsp_get_irq(s, s->uart_dev));
aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->timerctrl),
"aspeed.timerctrl",
@@ -283,8 +280,6 @@ static void aspeed_soc_ast27x0tsp_class_init(ObjectClass *klass,
dc->realize = aspeed_soc_ast27x0tsp_realize;
sc->valid_cpu_types = valid_cpu_types;
- sc->uarts_num = 13;
- sc->uarts_base = ASPEED_DEV_UART0;
sc->irqmap = aspeed_soc_ast27x0tsp_irqmap;
sc->memmap = aspeed_soc_ast27x0tsp_memmap;
}
diff --git a/hw/arm/aspeed_coprocessor_common.c b/hw/arm/aspeed_coprocessor_common.c
index 14e26bbe234e..f037d5b573fd 100644
--- a/hw/arm/aspeed_coprocessor_common.c
+++ b/hw/arm/aspeed_coprocessor_common.c
@@ -29,6 +29,9 @@ static const Property aspeed_coprocessor_properties[] = {
MemoryRegion *),
DEFINE_PROP_LINK("scu", AspeedCoprocessorState, scu, TYPE_ASPEED_SCU,
AspeedSCUState *),
+ DEFINE_PROP_LINK("uart", AspeedCoprocessorState, uart, TYPE_SERIAL_MM,
+ SerialMM *),
+ DEFINE_PROP_INT32("uart-dev", AspeedCoprocessorState, uart_dev, 0),
};
static void aspeed_coprocessor_class_init(ObjectClass *oc, const void *data)
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 07/16] hw/arm/aspeed_ast27x0-fc: Map FMC0 flash contents into CA35 boot ROM
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (5 preceding siblings ...)
2025-10-22 12:29 ` [PULL 06/16] hw/arm/ast27x0: Share single UART set " Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 08/16] hw/arm/aspeed_ast27x0-fc: Add VBOOTROM support Cédric Le Goater
` (9 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
This patch introduces a dedicated ca35_boot_rom memory region and
copies the FMC0 flash data into it.
The motivation is to support the upcoming vbootrom. The vbootrom
replaces the existing BOOTMCU (RISC-V 32 SPL) flow, which currently reads
the "image-bmc" from FMC_CS0 and loads the following components
into DRAM:
- Trusted Firmware-A
- OP-TEE OS
- u-boot-nodtb.bin
- u-boot.dtb
After loading, BOOTMCU releases the CA35 reset so that CA35 can start
executing Trusted Firmware-A.
The vbootrom follows the same sequence: CA35 fetches "image-bmc" from FMC0
flash at the SPI boot ROM base address (0x100000000), parses the FIT image,
loads each component into its designated DRAM location, and then jumps to
Trusted Firmware-A.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-8-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-fc.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 99af87dbd7bd..99c0b3415990 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -35,6 +35,7 @@ struct Ast2700FCState {
MemoryRegion ca35_memory;
MemoryRegion ca35_dram;
+ MemoryRegion ca35_boot_rom;
MemoryRegion ssp_memory;
MemoryRegion tsp_memory;
@@ -44,8 +45,6 @@ struct Ast2700FCState {
Aspeed27x0SoCState ca35;
Aspeed27x0CoprocessorState ssp;
Aspeed27x0CoprocessorState tsp;
-
- bool mmio_exec;
};
#define AST2700FC_BMC_RAM_SIZE (1 * GiB)
@@ -61,6 +60,9 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
Ast2700FCState *s = AST2700A1FC(machine);
AspeedSoCState *soc;
AspeedSoCClass *sc;
+ BlockBackend *fmc0 = NULL;
+ DeviceState *dev = NULL;
+ uint64_t rom_size;
object_initialize_child(OBJECT(s), "ca35", &s->ca35, "ast2700-a1");
soc = ASPEED_SOC(&s->ca35);
@@ -112,6 +114,14 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
ast2700fc_board_info.ram_size = machine->ram_size;
ast2700fc_board_info.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
+ dev = ssi_get_cs(soc->fmc.spi, 0);
+ fmc0 = dev ? m25p80_get_blk(dev) : NULL;
+
+ if (fmc0) {
+ rom_size = memory_region_size(&soc->spi_boot);
+ aspeed_install_boot_rom(soc, fmc0, &s->ca35_boot_rom, rom_size);
+ }
+
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
return true;
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 08/16] hw/arm/aspeed_ast27x0-fc: Add VBOOTROM support
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (6 preceding siblings ...)
2025-10-22 12:29 ` [PULL 07/16] hw/arm/aspeed_ast27x0-fc: Map FMC0 flash contents into CA35 boot ROM Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 09/16] tests/functional/aarch64/ast2700fc: Update test ASPEED SDK v09.08 Cédric Le Goater
` (8 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Introduces support for loading a vbootrom image into the dedicated vbootrom
memory region in the AST2700 Full Core machine.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-9-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-fc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 99c0b3415990..7be2e849274d 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -60,6 +60,7 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
Ast2700FCState *s = AST2700A1FC(machine);
AspeedSoCState *soc;
AspeedSoCClass *sc;
+ const char *bios_name = NULL;
BlockBackend *fmc0 = NULL;
DeviceState *dev = NULL;
uint64_t rom_size;
@@ -122,6 +123,10 @@ static bool ast2700fc_ca35_init(MachineState *machine, Error **errp)
aspeed_install_boot_rom(soc, fmc0, &s->ca35_boot_rom, rom_size);
}
+ /* VBOOTROM */
+ bios_name = machine->firmware ?: VBOOTROM_FILE_NAME;
+ aspeed_load_vbootrom(soc, bios_name, errp);
+
arm_load_kernel(ARM_CPU(first_cpu), machine, &ast2700fc_board_info);
return true;
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 09/16] tests/functional/aarch64/ast2700fc: Update test ASPEED SDK v09.08
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (7 preceding siblings ...)
2025-10-22 12:29 ` [PULL 08/16] hw/arm/aspeed_ast27x0-fc: Add VBOOTROM support Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 10/16] tests/functional/aarch64/ast2700fc: Add eth2 network interface check in PCIe test Cédric Le Goater
` (7 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-10-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
tests/functional/aarch64/test_aspeed_ast2700fc.py | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 28b66614d970..bcce0c8d4e53 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -36,9 +36,9 @@ def verify_openbmc_boot_and_login(self, name):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
- ASSET_SDK_V906_AST2700 = Asset(
- 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.06/ast2700-default-obmc.tar.gz',
- 'f1d53e0be8a404ecce3e105f72bc50fa4e090ad13160ffa91b10a6e0233a9dc6')
+ ASSET_SDK_V908_AST2700 = Asset(
+ 'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
+ 'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
def do_ast2700_i2c_test(self):
exec_command_and_wait_for_pattern(self,
@@ -66,7 +66,7 @@ def do_ast2700fc_ssp_test(self):
self.vm.set_console(console_index=1)
self.vm.launch()
- exec_command_and_wait_for_pattern(self, '\012', 'ssp:~$')
+ exec_command_and_wait_for_pattern(self, '\012', 'ssp_tsp:~$')
exec_command_and_wait_for_pattern(self, 'version',
'Zephyr version 3.7.1')
exec_command_and_wait_for_pattern(self, 'md 72c02000 1',
@@ -133,10 +133,10 @@ def start_ast2700fc_test(self, name):
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
- def test_aarch64_ast2700fc_sdk_v09_06(self):
+ def test_aarch64_ast2700fc_sdk_v09_08(self):
self.set_machine('ast2700fc')
- self.archive_extract(self.ASSET_SDK_V906_AST2700)
+ self.archive_extract(self.ASSET_SDK_V908_AST2700)
self.start_ast2700fc_test('ast2700-default')
self.verify_openbmc_boot_and_login('ast2700-default')
self.do_ast2700_i2c_test()
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 10/16] tests/functional/aarch64/ast2700fc: Add eth2 network interface check in PCIe test
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (8 preceding siblings ...)
2025-10-22 12:29 ` [PULL 09/16] tests/functional/aarch64/ast2700fc: Update test ASPEED SDK v09.08 Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 11/16] tests/functional/aarch64/ast2700fc: Move coprocessor image loading to common function Cédric Le Goater
` (6 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Enhance the AST2700 functional PCIe test to verify the network interface
configuration for eth2. This adds an additional command to check the IP
address assignment on eth2 to ensure network functionality is correctly
initialized in the test environment.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-11-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
tests/functional/aarch64/test_aspeed_ast2700fc.py | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index bcce0c8d4e53..843647e6c539 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -60,6 +60,9 @@ def do_ast2700_pcie_test(self):
'lspci -s 0002:01:00.0',
'0002:01:00.0 Ethernet controller: '
'Intel Corporation 82574L Gigabit Network Connection')
+ exec_command_and_wait_for_pattern(self,
+ 'ip addr show dev eth2',
+ 'inet 10.0.2.15/24')
def do_ast2700fc_ssp_test(self):
self.vm.shutdown()
@@ -135,6 +138,7 @@ def start_ast2700fc_test(self, name):
def test_aarch64_ast2700fc_sdk_v09_08(self):
self.set_machine('ast2700fc')
+ self.require_netdev('user')
self.archive_extract(self.ASSET_SDK_V908_AST2700)
self.start_ast2700fc_test('ast2700-default')
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 11/16] tests/functional/aarch64/ast2700fc: Move coprocessor image loading to common function
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (9 preceding siblings ...)
2025-10-22 12:29 ` [PULL 10/16] tests/functional/aarch64/ast2700fc: Add eth2 network interface check in PCIe test Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 12/16] tests/functional/aarch64/ast2700fc: Add vbootrom test Cédric Le Goater
` (5 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
This removes duplicate code in start_ast2700fc_test() and prepares for reuse in
upcoming VBOOTROM tests.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-12-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
.../aarch64/test_aspeed_ast2700fc.py | 22 ++++++++++---------
1 file changed, 12 insertions(+), 10 deletions(-)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 843647e6c539..9ab3d3269b2a 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -36,6 +36,17 @@ def verify_openbmc_boot_and_login(self, name):
exec_command_and_wait_for_pattern(self, 'root', 'Password:')
exec_command_and_wait_for_pattern(self, '0penBmc', f'root@{name}:~#')
+ def load_ast2700fc_coprocessor(self, name):
+ load_elf_list = {
+ 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
+ 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
+ }
+
+ for cpu_num, key in enumerate(load_elf_list, start=4):
+ file = load_elf_list[key]
+ self.vm.add_args('-device',
+ f'loader,file={file},cpu-num={cpu_num}')
+
ASSET_SDK_V908_AST2700 = Asset(
'https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.08/ast2700-default-obmc.tar.gz',
'eac3dc409b7ea3cd4b03d4792d3cebd469792ad893cb51e1d15f0fc20bd1e2cd')
@@ -123,16 +134,7 @@ def start_ast2700fc_test(self, name):
self.vm.add_args('-device',
f'loader,addr=0x430000000,cpu-num={i}')
- load_elf_list = {
- 'ssp': self.scratch_file(name, 'zephyr-aspeed-ssp.elf'),
- 'tsp': self.scratch_file(name, 'zephyr-aspeed-tsp.elf')
- }
-
- for cpu_num, key in enumerate(load_elf_list, start=4):
- file = load_elf_list[key]
- self.vm.add_args('-device',
- f'loader,file={file},cpu-num={cpu_num}')
-
+ self.load_ast2700fc_coprocessor(name)
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 12/16] tests/functional/aarch64/ast2700fc: Add vbootrom test
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (10 preceding siblings ...)
2025-10-22 12:29 ` [PULL 11/16] tests/functional/aarch64/ast2700fc: Move coprocessor image loading to common function Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 13/16] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Cédric Le Goater
` (4 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Jamin Lin, Cédric Le Goater
From: Jamin Lin <jamin_lin@aspeedtech.com>
Add start_ast2700fc_test_vbootrom() which boots the ast2700fc machine
with -bios ast27x0_bootrom.bin and reuses the coprocessor loader.
Add test_aarch64_ast2700fc_sdk_vbootrom_v09_08() to test the vbootrom
with ast2700fc machine.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015062210.3128710-13-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
tests/functional/aarch64/test_aspeed_ast2700fc.py | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/tests/functional/aarch64/test_aspeed_ast2700fc.py b/tests/functional/aarch64/test_aspeed_ast2700fc.py
index 9ab3d3269b2a..8dbc8f234f9c 100755
--- a/tests/functional/aarch64/test_aspeed_ast2700fc.py
+++ b/tests/functional/aarch64/test_aspeed_ast2700fc.py
@@ -138,6 +138,12 @@ def start_ast2700fc_test(self, name):
self.do_test_aarch64_aspeed_sdk_start(
self.scratch_file(name, 'image-bmc'))
+ def start_ast2700fc_test_vbootrom(self, name):
+ self.vm.add_args('-bios', 'ast27x0_bootrom.bin')
+ self.load_ast2700fc_coprocessor(name)
+ self.do_test_aarch64_aspeed_sdk_start(
+ self.scratch_file(name, 'image-bmc'))
+
def test_aarch64_ast2700fc_sdk_v09_08(self):
self.set_machine('ast2700fc')
self.require_netdev('user')
@@ -150,5 +156,14 @@ def test_aarch64_ast2700fc_sdk_v09_08(self):
self.do_ast2700fc_ssp_test()
self.do_ast2700fc_tsp_test()
+ def test_aarch64_ast2700fc_sdk_vbootrom_v09_08(self):
+ self.set_machine('ast2700fc')
+
+ self.archive_extract(self.ASSET_SDK_V908_AST2700)
+ self.start_ast2700fc_test_vbootrom('ast2700-default')
+ self.verify_openbmc_boot_and_login('ast2700-default')
+ self.do_ast2700fc_ssp_test()
+ self.do_ast2700fc_tsp_test()
+
if __name__ == '__main__':
QemuSystemTest.main()
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 13/16] hw/gpio: Add property for ASPEED GPIO in 32 bits basis
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (11 preceding siblings ...)
2025-10-22 12:29 ` [PULL 12/16] tests/functional/aarch64/ast2700fc: Add vbootrom test Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 14/16] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Cédric Le Goater
` (3 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Felix Wu, Andrew Jeffery, Cédric Le Goater
From: Felix Wu <flwu@google.com>
Added 32 bits property for ASPEED GPIO. Previously it can only be
access in bitwise manner.
The changes to qobject is to index gpios with array indices on top of
accessing with registers. This allows for easier gpio access,
especially in tests with complex behaviors that requires large number
of gpios at a time, like fault injection and networking behaviors.
Indexing multiple gpios at once allows qmp/side band client to no
longer hardcode and populate register names and manipulate them
faster.
Signed-off-by: Felix Wu <flwu@google.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/qemu-devel/20251015011830.1688468-2-lixiaoyan@google.com
[ clg: wrapped commit log lines ]
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/gpio/aspeed_gpio.c | 57 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 57 insertions(+)
diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c
index 609a556908f9..2d78bf9515c4 100644
--- a/hw/gpio/aspeed_gpio.c
+++ b/hw/gpio/aspeed_gpio.c
@@ -1308,6 +1308,57 @@ static void aspeed_gpio_2700_write(void *opaque, hwaddr offset,
}
/* Setup functions */
+static void aspeed_gpio_set_set(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ uint32_t set_val = 0;
+ AspeedGPIOState *s = ASPEED_GPIO(obj);
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ int set_idx = 0;
+
+ if (!visit_type_uint32(v, name, &set_val, errp)) {
+ return;
+ }
+
+ if (sscanf(name, "gpio-set[%d]", &set_idx) != 1) {
+ error_setg(errp, "%s: error reading %s", __func__, name);
+ return;
+ }
+
+ if (set_idx >= agc->nr_gpio_sets || set_idx < 0) {
+ error_setg(errp, "%s: invalid set_idx %s", __func__, name);
+ return;
+ }
+
+ aspeed_gpio_update(s, &s->sets[set_idx], set_val,
+ ~s->sets[set_idx].direction);
+}
+
+static void aspeed_gpio_get_set(Object *obj, Visitor *v,
+ const char *name, void *opaque,
+ Error **errp)
+{
+ uint32_t set_val = 0;
+ AspeedGPIOState *s = ASPEED_GPIO(obj);
+ AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s);
+ int set_idx = 0;
+
+ if (sscanf(name, "gpio-set[%d]", &set_idx) != 1) {
+ error_setg(errp, "%s: error reading %s", __func__, name);
+ return;
+ }
+
+ if (set_idx >= agc->nr_gpio_sets || set_idx < 0) {
+ error_setg(errp, "%s: invalid set_idx %s", __func__, name);
+ return;
+ }
+
+ set_val = s->sets[set_idx].data_value;
+ visit_type_uint32(v, name, &set_val, errp);
+}
+
+/****************** Setup functions ******************/
static const GPIOSetProperties ast2400_set_props[ASPEED_GPIO_MAX_NR_SETS] = {
[0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} },
[1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} },
@@ -1435,6 +1486,12 @@ static void aspeed_gpio_init(Object *obj)
g_free(name);
}
}
+
+ for (int i = 0; i < agc->nr_gpio_sets; i++) {
+ char *name = g_strdup_printf("gpio-set[%d]", i);
+ object_property_add(obj, name, "uint32", aspeed_gpio_get_set,
+ aspeed_gpio_set_set, NULL, NULL);
+ }
}
static const VMStateDescription vmstate_gpio_regs = {
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 14/16] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (12 preceding siblings ...)
2025-10-22 12:29 ` [PULL 13/16] hw/gpio: Add property for ASPEED GPIO in 32 bits basis Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 15/16] hw/arm/aspeed: ast2600-evb: Use w25q512jv flash model Cédric Le Goater
` (2 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Felix Wu, Cédric Le Goater
From: Felix Wu <flwu@google.com>
- Added qtests to test gpio-set property for ASPEED.
- Added function to get uint in qdict.
Signed-off-by: Felix Wu <flwu@google.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251015011830.1688468-3-lixiaoyan@google.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
include/qobject/qdict.h | 1 +
qobject/qdict.c | 13 ++++
tests/qtest/aspeed_gpio-test.c | 105 ++++++++++++++++++++++++++++++---
3 files changed, 110 insertions(+), 9 deletions(-)
diff --git a/include/qobject/qdict.h b/include/qobject/qdict.h
index 903e6e5462fb..861996f08dd6 100644
--- a/include/qobject/qdict.h
+++ b/include/qobject/qdict.h
@@ -57,6 +57,7 @@ void qdict_put_str(QDict *qdict, const char *key, const char *value);
double qdict_get_double(const QDict *qdict, const char *key);
int64_t qdict_get_int(const QDict *qdict, const char *key);
+uint64_t qdict_get_uint(const QDict *qdict, const char *key);
bool qdict_get_bool(const QDict *qdict, const char *key);
QList *qdict_get_qlist(const QDict *qdict, const char *key);
QDict *qdict_get_qdict(const QDict *qdict, const char *key);
diff --git a/qobject/qdict.c b/qobject/qdict.c
index a90ac9ae2f89..0dafe6d42179 100644
--- a/qobject/qdict.c
+++ b/qobject/qdict.c
@@ -209,6 +209,19 @@ int64_t qdict_get_int(const QDict *qdict, const char *key)
return qnum_get_int(qobject_to(QNum, qdict_get(qdict, key)));
}
+/**
+ * qdict_get_uint(): Get an unsigned integer mapped by 'key'
+ *
+ * This function assumes that 'key' exists and it stores a
+ * QNum representable as uint.
+ *
+ * Return unsigned integer mapped by 'key'.
+ */
+uint64_t qdict_get_uint(const QDict *qdict, const char *key)
+{
+ return qnum_get_uint(qobject_to(QNum, qdict_get(qdict, key)));
+}
+
/**
* qdict_get_bool(): Get a bool mapped by 'key'
*
diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c
index 12675d4cbba9..c2f9ca2298a7 100644
--- a/tests/qtest/aspeed_gpio-test.c
+++ b/tests/qtest/aspeed_gpio-test.c
@@ -27,28 +27,115 @@
#include "qemu/timer.h"
#include "qobject/qdict.h"
#include "libqtest-single.h"
+#include "qemu/typedefs.h"
#define AST2600_GPIO_BASE 0x1E780000
#define GPIO_ABCD_DATA_VALUE 0x000
#define GPIO_ABCD_DIRECTION 0x004
+static uint32_t qtest_qom_get_uint32(QTestState *s, const char *path,
+ const char *property)
+{
+ QDict *r;
+
+ uint32_t res;
+ r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': "
+ "{ 'path': %s, 'property': %s } }", path, property);
+ res = qdict_get_uint(r, "return");
+ qobject_unref(r);
+
+ return res;
+}
+
+static void qtest_qom_set_uint32(QTestState *s, const char *path,
+ const char *property, uint32_t value)
+{
+ QDict *r;
+
+ r = qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': "
+ "{ 'path': %s, 'property': %s, 'value': %" PRIu32 " } }",
+ path, property, value);
+ qobject_unref(r);
+}
+
+static const char *resp_get_error(QDict *r, const char* error_key)
+{
+ QDict *qdict;
+
+ g_assert(r);
+
+ qdict = qdict_get_qdict(r, "error");
+ if (qdict) {
+ return qdict_get_str(qdict, error_key);
+ }
+
+ return NULL;
+}
+
+static bool qtest_qom_check_error(QTestState *s, const char *path,
+ const char *property, const char *error_msg,
+ const char *error_msg_key)
+{
+ QDict *r;
+ bool b;
+
+ r = qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': "
+ "{ 'path': %s, 'property': %s } }", path, property);
+ b = g_str_equal(resp_get_error(r, error_msg_key), error_msg);
+ qobject_unref(r);
+
+ return b;
+}
+
static void test_set_colocated_pins(const void *data)
{
QTestState *s = (QTestState *)data;
-
+ const char path[] = "/machine/soc/gpio";
/*
* gpioV4-7 occupy bits within a single 32-bit value, so we want to make
* sure that modifying one doesn't affect the other.
*/
- qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true);
- qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false);
- qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true);
- qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false);
- g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV4"));
- g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV5"));
- g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV6"));
- g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV7"));
+ qtest_qom_set_bool(s, path, "gpioV4", true);
+ qtest_qom_set_bool(s, path, "gpioV5", false);
+ qtest_qom_set_bool(s, path, "gpioV6", true);
+ qtest_qom_set_bool(s, path, "gpioV7", false);
+ g_assert(qtest_qom_get_bool(s, path, "gpioV4"));
+ g_assert(!qtest_qom_get_bool(s, path, "gpioV5"));
+ g_assert(qtest_qom_get_bool(s, path, "gpioV6"));
+ g_assert(!qtest_qom_get_bool(s, path, "gpioV7"));
+
+ /*
+ * Testing the gpio-set[%d] properties, using individual gpio boolean
+ * properties to do cross check.
+ * We use gpioR4-7 for test, Setting them to be 0b1010.
+ */
+ qtest_qom_set_uint32(s, path, "gpio-set[4]", 0x0);
+ g_assert(qtest_qom_get_uint32(s, path, "gpio-set[4]") == 0x0);
+ qtest_qom_set_uint32(s, path, "gpio-set[4]", 0xa000);
+ g_assert(qtest_qom_get_uint32(s, path, "gpio-set[4]") == 0xa000);
+
+ g_assert(!qtest_qom_get_bool(s, path, "gpioR4"));
+ g_assert(qtest_qom_get_bool(s, path, "gpioR5"));
+ g_assert(!qtest_qom_get_bool(s, path, "gpioR6"));
+ g_assert(qtest_qom_get_bool(s, path, "gpioR7"));
+
+ /*
+ * Testing the invalid indexing, the response info should contain following
+ * info:
+ * {key: "class", value: "GenericError"}
+ *
+ * For pins, it should follow "gpio%2[A-Z]%1d" or "gpio%3[18A-E]%1d" format.
+ */
+ const char error_msg[] = "GenericError";
+ const char error_msg_key[] = "class";
+
+ g_assert(qtest_qom_check_error(s, path, "gpioR+1", error_msg,
+ error_msg_key));
+ g_assert(qtest_qom_check_error(s, path, "gpio-set[99]", error_msg,
+ error_msg_key));
+ g_assert(qtest_qom_check_error(s, path, "gpio-set[-3]", error_msg,
+ error_msg_key));
}
static void test_set_input_pins(const void *data)
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 15/16] hw/arm/aspeed: ast2600-evb: Use w25q512jv flash model
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (13 preceding siblings ...)
2025-10-22 12:29 ` [PULL 14/16] tests/qtest: Add qtest for for ASPEED GPIO gpio-set property Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 12:29 ` [PULL 16/16] hw/arm/aspeed: Remove ast2700fc self-aliasing Cédric Le Goater
2025-10-22 14:31 ` [PULL 00/16] aspeed queue Richard Henderson
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Cédric Le Goater, Jamin Lin
The ast2600-evb machine model is using the "mx66u51235f" flash model,
which has issues with recent Linux kernels (6.15+) when reading SFDP
data.
Change the flash model to "w25q512jv", which is the model present on
some ast2600a3 EVB board and is known to work correctly with recent
kernels. Adjust the corresponding qtest to reflect the new JEDEC ID of
the w25q512jv flash.
Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
Link: https://lore.kernel.org/qemu-devel/20251016212437.1046135-1-clg@redhat.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed.c | 4 ++--
tests/qtest/aspeed_smc-test.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 21ee62f75044..1bc9e534ba49 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -1592,8 +1592,8 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
amc->soc_name = "ast2600-a3";
amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
- amc->fmc_model = "mx66u51235f";
- amc->spi_model = "mx66u51235f";
+ amc->fmc_model = "w25q512jv";
+ amc->spi_model = "w25q512jv";
amc->num_cs = 1;
amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
ASPEED_MAC3_ON;
diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c
index 52a00e6f0a7e..50a87e625001 100644
--- a/tests/qtest/aspeed_smc-test.c
+++ b/tests/qtest/aspeed_smc-test.c
@@ -134,10 +134,10 @@ static void test_ast2600_evb(AspeedSMCTestData *data)
"-drive file=%s,format=raw,if=mtd",
data->tmp_path);
- /* fmc cs0 with mx66u51235f flash */
+ /* fmc cs0 with w25q512jv flash */
data->flash_base = 0x20000000;
data->spi_base = 0x1E620000;
- data->jedec_id = 0xc2253a;
+ data->jedec_id = 0xef4020;
data->cs = 0;
data->node = "/machine/soc/fmc/ssi.0/child[0]";
/* beyond 16MB */
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* [PULL 16/16] hw/arm/aspeed: Remove ast2700fc self-aliasing
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (14 preceding siblings ...)
2025-10-22 12:29 ` [PULL 15/16] hw/arm/aspeed: ast2600-evb: Use w25q512jv flash model Cédric Le Goater
@ 2025-10-22 12:29 ` Cédric Le Goater
2025-10-22 14:31 ` [PULL 00/16] aspeed queue Richard Henderson
16 siblings, 0 replies; 20+ messages in thread
From: Cédric Le Goater @ 2025-10-22 12:29 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Philippe Mathieu-Daudé, Cédric Le Goater
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Remove pointless alias to the very same machine:
$ qemu-system-aarch64 -M help | fgrep ast2700fc
ast2700fc ast2700 full core support (alias of ast2700fc)
ast2700fc ast2700 full core support
Fixes: a74faf35efc ("hw/arm: Introduce ASPEED AST2700 A1 full core machine")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20251021110427.93991-1-philmd@linaro.org
Signed-off-by: Cédric Le Goater <clg@redhat.com>
---
hw/arm/aspeed_ast27x0-fc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 7be2e849274d..580ac5f7a124 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -207,7 +207,6 @@ static void ast2700fc_class_init(ObjectClass *oc, const void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
- mc->alias = "ast2700fc";
mc->desc = "ast2700 full core support";
mc->init = ast2700fc_init;
mc->no_floppy = 1;
--
2.51.0
^ permalink raw reply related [flat|nested] 20+ messages in thread* Re: [PULL 00/16] aspeed queue
2025-10-22 12:29 [PULL 00/16] aspeed queue Cédric Le Goater
` (15 preceding siblings ...)
2025-10-22 12:29 ` [PULL 16/16] hw/arm/aspeed: Remove ast2700fc self-aliasing Cédric Le Goater
@ 2025-10-22 14:31 ` Richard Henderson
16 siblings, 0 replies; 20+ messages in thread
From: Richard Henderson @ 2025-10-22 14:31 UTC (permalink / raw)
To: qemu-devel
On 10/22/25 07:29, Cédric Le Goater wrote:
> The following changes since commit 3c0b42c68f98fb276fa248012642be8cbf2cab70:
>
> Merge tag 'pull-request-2025-10-21' ofhttps://gitlab.com/thuth/qemu into staging (2025-10-21 08:59:35 -0500)
>
> are available in the Git repository at:
>
> https://github.com/legoater/qemu/ tags/pull-aspeed-20251022
>
> for you to fetch changes up to d7bd42a740d0e8887540d7b450d0bdb2d6ba31ea:
>
> hw/arm/aspeed: Remove ast2700fc self-aliasing (2025-10-22 08:14:09 +0200)
>
> ----------------------------------------------------------------
> aspeed queue:
>
> * Improve AST2700 co-processor models
> * Add vbootrom support to the ast2700fc multi-soc machine
> * Bump SDK version to v09.08 for the ast2700fc machine
> * Add 32 bits property for Aspeed GPIOs
> * Change ast2600-evb machine flash model to w25q512jv
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate.
r~
^ permalink raw reply [flat|nested] 20+ messages in thread