From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBCA1CCD193 for ; Thu, 23 Oct 2025 10:03:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vBs9k-0001Y4-10; Thu, 23 Oct 2025 06:02:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9h-0001X9-HR; Thu, 23 Oct 2025 06:02:49 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vBs9f-0003D7-8G; Thu, 23 Oct 2025 06:02:49 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 23 Oct 2025 18:01:55 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 23 Oct 2025 18:01:55 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 12/13] hw/arm/aspeed: Split Supermicro X11SPI machine into a separate file for maintainability Date: Thu, 23 Oct 2025 18:01:45 +0800 Message-ID: <20251023100150.295370-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251023100150.295370-1-jamin_lin@aspeedtech.com> References: <20251023100150.295370-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit moves the Supermicro X11SPI BMC machine definition from aspeed.c into a new standalone file aspeed_ast2500_supermicro-x11spi.c, and adds a dedicated I²C initialization function for the platform. The refactor continues the effort to modularize Aspeed platform support, ensuring each machine model is defined in its own source file. This improves code organization, readability, and simplifies maintenance when adding or modifying platform-specific behavior. Previously, the Supermicro X11SPI machine reused palmetto_bmc_i2c_init() for its I²C setup. To make the machine definition fully self-contained, the function was copied and renamed to supermicro_x11spi_bmc_i2c_init(). This ensures that the machine can evolve independently without depending on Palmetto’s board logi Key updates include: - Moved SUPERMICRO_X11SPI_BMC_HW_STRAP1 macro and machine class init (aspeed_machine_supermicro_x11spi_bmc_class_init) into a new file. - Added new function supermicro_x11spi_bmc_i2c_init() copied from palmetto_bmc_i2c_init() for independent control. - Updated the machine definition to use the new I²C init function. - Registered the new source file in meson.build. - Removed all Supermicro X11SPI-related definitions from aspeed.c. No functional changes. Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 32 ---------- hw/arm/aspeed_ast2500_supermicro-x11spi.c | 76 +++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 77 insertions(+), 32 deletions(-) create mode 100644 hw/arm/aspeed_ast2500_supermicro-x11spi.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a97d037acb..3618f01ea2 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -70,16 +70,6 @@ static struct arm_boot_info aspeed_board_binfo = { SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) -/* TODO: Find the actual hardware value */ -#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ - AST2500_HW_STRAP1_DEFAULTS | \ - SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ - SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ - SCU_AST2500_HW_STRAP_UART_DEBUG | \ - SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ - SCU_HW_STRAP_SPI_WIDTH | \ - SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) - /* AST2500 evb hardware value: 0xF100C2E6 */ #define AST2500_EVB_HW_STRAP1 (( \ AST2500_HW_STRAP1_DEFAULTS | \ @@ -1186,24 +1176,6 @@ static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } -static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - - mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; - amc->soc_name = "ast2500-a1"; - amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; - amc->fmc_model = "mx25l25635e"; - amc->spi_model = "mx25l25635e"; - amc->num_cs = 1; - amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; - amc->i2c_init = palmetto_bmc_i2c_init; - mc->default_ram_size = 512 * MiB; - aspeed_machine_class_init_cpus_defaults(mc); -} - static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, const void *data) { @@ -1574,10 +1546,6 @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("supermicrox11-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_supermicrox11_bmc_class_init, - }, { - .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), - .parent = TYPE_ASPEED_MACHINE, - .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, }, { .name = MACHINE_TYPE_NAME("ast2500-evb"), .parent = TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2500_supermicro-x11spi.c new file mode 100644 index 0000000000..49332463c4 --- /dev/null +++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c @@ -0,0 +1,76 @@ +/* + * Supermicro X11 SPI + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/i2c/smbus_eeprom.h" + +/* TODO: Find the actual hardware value */ +#define SUPERMICRO_X11SPI_BMC_HW_STRAP1 ( \ + AST2500_HW_STRAP1_DEFAULTS | \ + SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \ + SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \ + SCU_AST2500_HW_STRAP_UART_DEBUG | \ + SCU_AST2500_HW_STRAP_DDR4_ENABLE | \ + SCU_HW_STRAP_SPI_WIDTH | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN)) + +static void supermicro_x11spi_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = bmc->soc; + DeviceState *dev; + uint8_t *eeprom_buf = g_malloc0(32 * 1024); + + /* + * The palmetto platform expects a ds3231 RTC but a ds1338 is + * enough to provide basic RTC features. Alarms will be missing + */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68); + + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, + eeprom_buf); + + /* add a TMP423 temperature sensor */ + dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), + "tmp423", 0x4c)); + object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort); + object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort); + object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort); + object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); +} + +static void aspeed_machine_supermicro_x11spi_bmc_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Supermicro X11 SPI BMC (ARM1176)"; + amc->soc_name = "ast2500-a1"; + amc->hw_strap1 = SUPERMICRO_X11SPI_BMC_HW_STRAP1; + amc->fmc_model = "mx25l25635e"; + amc->spi_model = "mx25l25635e"; + amc->num_cs = 1; + amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON; + amc->i2c_init = supermicro_x11spi_bmc_i2c_init; + mc->default_ram_size = 512 * MiB; + aspeed_machine_class_init_cpus_defaults(mc); +} + +static const TypeInfo aspeed_ast2500_supermicro_x11spi_types[] = { + { + .name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_supermicro_x11spi_bmc_class_init, + } +}; + +DEFINE_TYPES(aspeed_ast2500_supermicro_x11spi_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index fdb825fd0e..f788baabeb 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -48,6 +48,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2500_g220a.c', 'aspeed_ast2500_romulus.c', 'aspeed_ast2500_sonorapass.c', + 'aspeed_ast2500_supermicro-x11spi.c', 'aspeed_ast2500_tiogapass.c', 'aspeed_ast2500_witherspoon.c', 'aspeed_ast2500_yosemitev2.c', -- 2.43.0