From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1FE63CCD1AB for ; Fri, 24 Oct 2025 06:37:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vCBP0-0004D6-5a; Fri, 24 Oct 2025 02:35:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vCBOx-00046j-VH for qemu-devel@nongnu.org; Fri, 24 Oct 2025 02:35:51 -0400 Received: from mgamail.intel.com ([198.175.65.20]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vCBOw-000401-0I for qemu-devel@nongnu.org; Fri, 24 Oct 2025 02:35:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1761287750; x=1792823750; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Y8zhy26akKwdW2BhI+hvLWp8vFtvjafeaMR+Q2ZDdtQ=; b=fucPljV8TYbPWqUfyNurIf9VuZ/0K9KjNiZIpRJOrS0l9xT3LxSVhHr7 6I+cuf/xFNkXVWCg9APo7E9D58XzR/Kd0W3XHvY5aGkGgQ5cW7KWJiSn2 ikFZB8Xmh5EIpq+veeRmFEw3f1vR3cg1wGsUxubG9emGm2cpk2dHVfKic /0168oo0OhzZK6UWQ4NIKyIMh9ornbNtHebeHr6BttcNUvEff/NL2SzYP H5OcoHORdNLrf4begtGrKWAY9N9pU4W6WfQhFn6VKjrX+gN1O//12qV2G qNfGKuqRxwxCX/q6sYI2aANaD08CZk8dzgOB0BmWMq8o0CjL08z+8epDP Q==; X-CSE-ConnectionGUID: zwF0MxRqR/K0XBhNVkJI5g== X-CSE-MsgGUID: 8Dn4zBw6RX+8S/0a65kNLQ== X-IronPort-AV: E=McAfee;i="6800,10657,11586"; a="63170933" X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="63170933" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Oct 2025 23:35:48 -0700 X-CSE-ConnectionGUID: h5zgwAcYRXCJymnotI8q0w== X-CSE-MsgGUID: xvT4b0YwQmyerxvlECQr1w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,251,1754982000"; d="scan'208";a="184276147" Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by fmviesa006.fm.intel.com with ESMTP; 23 Oct 2025 23:35:45 -0700 From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Chenyi Qiang , Xiaoyao Li , Farrah Chen , Zhao Liu Subject: [PATCH v3 18/20] i386/cpu: Enable cet-ss & cet-ibt for supported CPU models Date: Fri, 24 Oct 2025 14:56:30 +0800 Message-Id: <20251024065632.1448606-19-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251024065632.1448606-1-zhao1.liu@intel.com> References: <20251024065632.1448606-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=198.175.65.20; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Add new versioned CPU models for Sapphire Rapids, Sierra Forest, Granite Rapids and Clearwater Forest, to enable shadow stack and indirect branch tracking. Tested-by: Farrah Chen Signed-off-by: Zhao Liu --- target/i386/cpu.c | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9a1001c47891..73026d5bce91 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5161,6 +5161,17 @@ static const X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ }, } }, + { + .version = 5, + .note = "with cet-ss and cet-ibt", + .props = (PropValue[]) { + { "cet-ss", "on" }, + { "cet-ibt", "on" }, + { "vmx-exit-save-cet", "on" }, + { "vmx-entry-load-cet", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ } } }, @@ -5323,6 +5334,17 @@ static const X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ }, } }, + { + .version = 4, + .note = "with cet-ss and cet-ibt", + .props = (PropValue[]) { + { "cet-ss", "on" }, + { "cet-ibt", "on" }, + { "vmx-exit-save-cet", "on" }, + { "vmx-entry-load-cet", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ }, }, }, @@ -5477,6 +5499,17 @@ static const X86CPUDefinition builtin_x86_defs[] = { { /* end of list */ }, } }, + { + .version = 4, + .note = "with cet-ss and cet-ibt", + .props = (PropValue[]) { + { "cet-ss", "on" }, + { "cet-ibt", "on" }, + { "vmx-exit-save-cet", "on" }, + { "vmx-entry-load-cet", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ }, }, }, @@ -5612,6 +5645,17 @@ static const X86CPUDefinition builtin_x86_defs[] = { .model_id = "Intel Xeon Processor (ClearwaterForest)", .versions = (X86CPUVersionDefinition[]) { { .version = 1 }, + { + .version = 2, + .note = "with cet-ss and cet-ibt", + .props = (PropValue[]) { + { "cet-ss", "on" }, + { "cet-ibt", "on" }, + { "vmx-exit-save-cet", "on" }, + { "vmx-entry-load-cet", "on" }, + { /* end of list */ }, + } + }, { /* end of list */ }, }, }, -- 2.34.1