From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 874B9CCD1BF for ; Sat, 25 Oct 2025 14:27:50 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vCfEk-0003zk-3g; Sat, 25 Oct 2025 10:27:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vCdZF-0001bW-HY for qemu-devel@nongnu.org; Sat, 25 Oct 2025 08:40:21 -0400 Received: from sg-1-21.ptr.blmpb.com ([118.26.132.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vCdZ8-0003jW-1G for qemu-devel@nongnu.org; Sat, 25 Oct 2025 08:40:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=openatom-club.20200927.dkim.feishu.cn; t=1761395938; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=AU494Ql8nJkePViZNHSEXIwXrMVwc7XucyPOLWHk9bw=; b=rwz/T7I2+CgCRYXhmRauLga7V1ZJb7wNvH0WnOKtZ2zPkXvA5lJrlyq3VeYoOvxNpzZyVX 9z3gM2OOZIUeWLsDNmHL9/9BX/0KqvS6+yuvkupG9nh+RReWeEWjxsS3BXcem2gKpGBEQj ffGcfiyFyzpI36sCoPuqkUGOxHR0bmTSxIYWmSRIrOZnlmxCJPn/lpWpoMwKZyihvSE92o zCMqplOpxRtOsmIopCZ7qgHQgkIc7KfhwCLvjMqswT1KiSd8GmHi9w248kQbH25CBIwAvx vzMYRk4h6GYsdc23yUDTzWXZ1okXggxifZoMZmfkntCzJTGXIRu95wS+e0rXNw== X-Lms-Return-Path: Content-Type: text/plain; charset=UTF-8 Received: from nyaos.localdomain ([114.249.194.57]) by smtp.feishu.cn with ESMTPS; Sat, 25 Oct 2025 20:38:56 +0800 X-Mailer: git-send-email 2.43.0 Date: Sat, 25 Oct 2025 12:38:50 +0000 Mime-Version: 1.0 X-Original-From: chenmiao From: "chenmiao" Subject: [RFC 2/5] rust: hw: core: Add rust bindings/funcs for i2c bus Message-Id: <20251025123853.63139-3-chenmiao@openatom.club> Content-Transfer-Encoding: quoted-printable To: , , , Cc: , , , "Chao Liu" Received-SPF: pass client-ip=118.26.132.21; envelope-from=chenmiao@openatom.club; helo=sg-1-21.ptr.blmpb.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sat, 25 Oct 2025 10:27:12 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We have implemented the I2CBus and I2CSlave infrastructure in Rust by refer= ring to the SysBus device model. Initially, we assumed that the I2CBus was at the same hierarchical level as= the PL011 device. Therefore, we followed the implementation paradigm of the PL0= 11 device as a reference. However, in the end, we discovered that the I2CBus i= s actually at the same level as the SysBus. As a result, we adopted the bindi= ng implementation paradigm used for SysBus devices. With this adjustment, we successfully compiled the code locally. During the implementation process, we found that the current two paradigms = in Rust =E2=80=94 bindings and impl =E2=80=94 are extremely complex and lack c= omprehensive documentation. There is no clear explanation as to why Bus and Device model= s need to be implemented using different approaches. Furthermore, the implementation of Bus and Device following these paradigms still has many limitations. At present, at least vmstate is not easily supported. Signed-off-by: Chao Liu Signed-off-by: chenmiao --- rust/hw/core/meson.build | 1 + rust/hw/core/src/i2cbus.rs | 291 +++++++++++++++++++++++++++++++++++++ rust/hw/core/src/lib.rs | 3 + rust/hw/core/wrapper.h | 1 + 4 files changed, 296 insertions(+) create mode 100644 rust/hw/core/src/i2cbus.rs diff --git a/rust/hw/core/meson.build b/rust/hw/core/meson.build index efcda50..7c44786 100644 --- a/rust/hw/core/meson.build +++ b/rust/hw/core/meson.build @@ -52,6 +52,7 @@ _hwcore_rs =3D static_library( 'src/bindings.rs', 'src/bus.rs', 'src/irq.rs', + 'src/i2cbus.rs', 'src/qdev.rs', 'src/sysbus.rs', ], diff --git a/rust/hw/core/src/i2cbus.rs b/rust/hw/core/src/i2cbus.rs new file mode 100644 index 0000000..c026955 --- /dev/null +++ b/rust/hw/core/src/i2cbus.rs @@ -0,0 +1,291 @@ +// Copyright 2025 HUST OpenAtom Open Source Club. +// Author(s): Chao Liu +// Author(s): Chen Miao +// SPDX-License-Identifier: GPL-2.0-or-later + +//! Bindings to access `i2c` functionality from Rust. + +use std::ffi::CStr; + +pub use bindings::I2CSlaveClass; +use common::Opaque; +use qom::{prelude::*, Owned}; +use util::Result; + +use crate::{ + bindings, + bus::{BusClass, BusState}, + qdev::{DeviceImpl, DeviceState}, +}; + +/// A safe wrapper around [`bindings::I2CBus`]. +#[repr(transparent)] +#[derive(Debug, common::Wrapper)] +pub struct I2CBus(Opaque); + +unsafe impl Send for I2CBus {} +unsafe impl Sync for I2CBus {} + +unsafe impl ObjectType for I2CBus { + type Class =3D BusClass; + const TYPE_NAME: &'static CStr =3D + unsafe { CStr::from_bytes_with_nul_unchecked(bindings::TYPE_I2C_BU= S) }; +} + +qom_isa!(I2CBus: BusState, Object); + +// TODO: add virtual methods +pub trait I2CBusImpl: DeviceImpl + IsA {} + +/// Trait for methods of [`I2CBus`] and its subclasses. +pub trait I2CBusMethods: ObjectDeref +where + Self::Target: IsA, +{ + /// Initialize an I2C bus + fn init_bus(&self, parent: &DeviceState, name: &str) -> *mut bindings:= :I2CBus { + assert!(bql::is_locked()); + unsafe { bindings::i2c_init_bus(parent.as_mut_ptr(), name.as_ptr()= .cast()) } + } + + /// Start a transfer on an I2C bus + fn start_transfer(&self, address: u8, is_recv: bool) -> i32 { + assert!(bql::is_locked()); + unsafe { bindings::i2c_start_transfer(self.upcast().as_mut_ptr(), = address, is_recv) } + } + + /// Start a receive transfer on an I2C bus + fn start_recv(&self, address: u8) -> i32 { + assert!(bql::is_locked()); + unsafe { bindings::i2c_start_recv(self.upcast().as_mut_ptr(), addr= ess) } + } + + /// Start a send transfer on an I2C bus + fn start_send(&self, address: u8) -> i32 { + assert!(bql::is_locked()); + unsafe { bindings::i2c_start_send(self.upcast().as_mut_ptr(), addr= ess) } + } + + /// Start an asynchronous send transfer on an I2C bus + fn start_send_async(&self, address: u8) -> i32 { + assert!(bql::is_locked()); + unsafe { bindings::i2c_start_send_async(self.upcast().as_mut_ptr()= , address) } + } + + /// End a transfer on an I2C bus + fn end_transfer(&self) { + assert!(bql::is_locked()); + unsafe { bindings::i2c_end_transfer(self.upcast().as_mut_ptr()) } + } + + /// Send NACK on an I2C bus + fn nack(&self) { + assert!(bql::is_locked()); + unsafe { bindings::i2c_nack(self.upcast().as_mut_ptr()) } + } + + /// Send ACK on an I2C bus + fn ack(&self) { + assert!(bql::is_locked()); + unsafe { bindings::i2c_ack(self.upcast().as_mut_ptr()) } + } + + /// Send data on an I2C bus + fn send(&self, data: u8) -> i32 { + assert!(bql::is_locked()); + unsafe { bindings::i2c_send(self.upcast().as_mut_ptr(), data) } + } + + /// Send data asynchronously on an I2C bus + fn send_async(&self, data: u8) -> i32 { + assert!(bql::is_locked()); + unsafe { bindings::i2c_send_async(self.upcast().as_mut_ptr(), data= ) } + } + + /// Receive data from an I2C bus + fn recv(&self) -> u8 { + assert!(bql::is_locked()); + unsafe { bindings::i2c_recv(self.upcast().as_mut_ptr()) } + } + + /// Check if the I2C bus is busy. + /// + /// Returns `true` if the bus is busy, `false` otherwise. + fn is_busy(&self) -> bool { + assert!(bql::is_locked()); + unsafe { bindings::i2c_bus_busy(self.upcast().as_mut_ptr()) !=3D 0= } + } + + /// Schedule pending master on an I2C bus + fn schedule_pending_master(&self) { + assert!(bql::is_locked()); + unsafe { bindings::i2c_schedule_pending_master(self.upcast().as_mu= t_ptr()) } + } + + /// Sets the I2C bus master. + /// + /// # Safety + /// + /// This function is unsafe because: + /// - `bh` must be a valid pointer to a `QEMUBH`. + /// - The caller must ensure that `self` is in a valid state. + /// - The caller must guarantee no data races occur during execution. + unsafe fn set_master(&self, bh: *mut bindings::QEMUBH) { + assert!(bql::is_locked()); + unsafe { bindings::i2c_bus_master(self.upcast().as_mut_ptr(), bh) = } + } + + /// Release an I2C bus + fn release(&self) { + assert!(bql::is_locked()); + unsafe { bindings::i2c_bus_release(self.upcast().as_mut_ptr()) } + } +} + +impl I2CBusMethods for R where R::Target: IsA {} + +/// A safe wrapper around [`bindings::I2CSlave`]. +#[repr(transparent)] +#[derive(Debug, common::Wrapper)] +pub struct I2CSlave(Opaque); + +unsafe impl Send for I2CSlave {} +unsafe impl Sync for I2CSlave {} + +unsafe impl ObjectType for I2CSlave { + type Class =3D I2CSlaveClass; + const TYPE_NAME: &'static CStr =3D + unsafe { CStr::from_bytes_with_nul_unchecked(bindings::TYPE_I2C_SL= AVE) }; +} + +qom_isa!(I2CSlave: DeviceState, Object); + +// TODO: add virtual methods +pub trait I2CSlaveImpl: DeviceImpl + IsA { + /// Master to slave. Returns non-zero for a NAK, 0 for success. + const SEND: Option Result> =3D None; + + /// Master to slave (asynchronous). Receiving slave must call `i2c_ack= ()`. + const SEND_ASYNC: Option Result<()>> =3D None; + + /// Slave to master. This cannot fail, the device should always return= something here. + const RECV: Option Result> =3D None; + + /// Notify the slave of a bus state change. For start event, + /// returns non-zero to NAK an operation. For other events the + /// return code is not used and should be zero. + const EVENT: Option Result> = =3D None; + + /// Check if this device matches the address provided. Returns bool of + /// true if it matches (or broadcast), and updates the device list, fa= lse + /// otherwise. + /// + /// If broadcast is true, match should add the device and return true. + type AddressMatcher; + const MATCH_AND_ADD: Option =3D None; +} + +impl I2CSlaveClass { + /// Fill in the virtual methods of `I2CSlaveClass` based on the + /// definitions in the `I2CSlaveImpl` trait. + pub fn class_init(self: &mut I2CSlaveClass) { + self.parent_class.class_init::(); + } +} + +/// Trait for methods of [`I2CSlave`] and its subclasses. +pub trait I2CSlaveMethods: ObjectDeref +where + Self::Target: IsA, +{ + /// Create an I2C slave device on the heap. + /// + /// # Arguments + /// * `name` - a device type name + /// * `addr` - I2C address of the slave when put on a bus + /// + /// This only initializes the device state structure and allows + /// properties to be set. Type `name` must exist. The device still + /// needs to be realized. + fn init_new(name: &str, addr: u8) -> Owned { + assert!(bql::is_locked()); + unsafe { + let slave =3D bindings::i2c_slave_new(name.as_ptr().cast(), ad= dr); + Owned::from(I2CSlave::from_raw(slave)) + } + } + + /// Create and realize an I2C slave device on the heap. + /// + /// # Arguments + /// * `bus` - I2C bus to put it on + /// * `name` - I2C slave device type name + /// * `addr` - I2C address of the slave when put on a bus + /// + /// Create the device state structure, initialize it, put it on the + /// specified `bus`, and drop the reference to it (the device is reali= zed). + fn create_simple(&self, bus: &I2CBus, name: &str, addr: u8) -> Owned { + assert!(bql::is_locked()); + unsafe { + let slave =3D + bindings::i2c_slave_create_simple(bus.as_mut_ptr(), name.a= s_ptr().cast(), addr); + Owned::from(I2CSlave::from_raw(slave)) + } + } + + /// Set the I2C bus address of a slave device + /// + /// # Arguments + /// * `address` - I2C address of the slave when put on a bus + fn set_address(&self, address: u8) { + assert!(bql::is_locked()); + unsafe { bindings::i2c_slave_set_address(self.upcast().as_mut_ptr(= ), address) } + } + + /// Get the I2C bus address of a slave device + fn get_address(&self) -> u8 { + assert!(bql::is_locked()); + // SAFETY: the BQL ensures that no one else writes to the I2CSlave= structure, + // and the I2CSlave must be initialized to get an IsA. + let slave =3D unsafe { *self.upcast().as_ptr() }; + slave.address + } +} + +impl I2CSlaveMethods for R where R::Target: IsA = {} + +/// Enum representing I2C events +#[repr(u32)] +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum I2CEvent { + StartRecv =3D 0, + StartSend =3D 1, + StartSendAsync =3D 2, + Finish =3D 3, + Nack =3D 4, +} + +impl From for I2CEvent { + fn from(event: bindings::i2c_event) -> Self { + match event { + bindings::I2C_START_RECV =3D> I2CEvent::StartRecv, + bindings::I2C_START_SEND =3D> I2CEvent::StartSend, + bindings::I2C_START_SEND_ASYNC =3D> I2CEvent::StartSendAsync, + bindings::I2C_FINISH =3D> I2CEvent::Finish, + bindings::I2C_NACK =3D> I2CEvent::Nack, + _ =3D> panic!("Unknown I2C event: {event}"), + } + } +} + +impl From for bindings::i2c_event { + fn from(event: I2CEvent) -> Self { + match event { + I2CEvent::StartRecv =3D> bindings::I2C_START_RECV, + I2CEvent::StartSend =3D> bindings::I2C_START_SEND, + I2CEvent::StartSendAsync =3D> bindings::I2C_START_SEND_ASYNC, + I2CEvent::Finish =3D> bindings::I2C_FINISH, + I2CEvent::Nack =3D> bindings::I2C_NACK, + } + } +} diff --git a/rust/hw/core/src/lib.rs b/rust/hw/core/src/lib.rs index 10cc516..fb0ee82 100644 --- a/rust/hw/core/src/lib.rs +++ b/rust/hw/core/src/lib.rs @@ -16,3 +16,6 @@ =20 mod bus; pub use bus::*; + +mod i2cbus; +pub use i2cbus::*; diff --git a/rust/hw/core/wrapper.h b/rust/hw/core/wrapper.h index 3bdbd12..399be59 100644 --- a/rust/hw/core/wrapper.h +++ b/rust/hw/core/wrapper.h @@ -30,3 +30,4 @@ typedef enum memory_order { #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" #include "hw/irq.h" +#include "hw/i2c/i2c.h" --=20 2.43.0