[PATCH v2 0/4] target/i386: Add support for Zhaoxin Shijidadao vCPU models

[Ewan Hai <ewanhai-oc@zhaoxin.com>]

This patchset introduces cache enumeration and two vCPU models (Client          
and Server) for the Zhaoxin "Shijidadao" architecture. With these               
additions, QEMU can expose the core identity and features of this               
architecture without relying on host-passthrough.

Key points for maintainers to review:

1. The Shijidadao-Client model leverages QEMU's inherent versioning mechanism.
.version = 1 represents the first hardware revision, while a new version = 2
captures the second revision with distinct feature sets. This approach allows
both revisions to be covered by a single CPU model, aligned with QEMU's
existing versioning logic.

2. The Shijidadao-Server model enables the 'core-capability' bit by default.
Since KVM does not yet virtualize the corresponding MSR, guidance on whether
this setting should remain enabled is requested.

---

Changes Since v1:
- Incorporated Zhao Liu's suggested patch that introduces the cpuid_0x1f option.
- Dropped explicit x-force-cpuid-0x1f property declarations from both
Shijidadao-Server and Shijidadao-Client models, since the new option provides
a cleaner solution.
- Updated commit messages for the Client and Server patches to remove
references to the earlier x-force-cpuid-0x1f approach.

---

Ewan Hai (3):
  target/i386: Add cache model for Zhaoxin Shijidadao vCPUs
  target/i386: Introduce Zhaoxin Shijidadao-Client CPU model
  target/i386: Introduce Zhaoxin Shijidadao-Server CPU model

Zhao Liu (1):
  target/i386: Add an option in X86CPUDefinition to control CPUID 0x1f

 target/i386/cpu.c | 380 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 380 insertions(+)

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2.34.1