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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952df62dsm15473844f8f.45.2025.10.27.06.31.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 27 Oct 2025 06:31:42 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , "Michael S. Tsirkin" , Richard Henderson , Marcel Apfelbaum , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 2/4] hw/pci-host/astro: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 14:30:35 +0100 Message-ID: <20251027133037.70487-3-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027133037.70487-1-philmd@linaro.org> References: <20251027133037.70487-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Avoid duplicating code, clear the "config-reg-check-high-bit" property in .instance_init() in order to re-use the generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/astro.c | 35 ++++++++--------------------------- hw/pci-host/trace-events | 2 -- 2 files changed, 8 insertions(+), 29 deletions(-) diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 0bd66ab3de3..110070486d7 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -230,32 +230,6 @@ static const MemoryRegionOps elroy_chip_ops = { }; -/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */ - -static uint64_t elroy_config_data_read(void *opaque, hwaddr addr, unsigned len) -{ - uint64_t val; - - PCIHostState *s = opaque; - val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); - trace_elroy_pci_config_data_read(s->config_reg | (addr & 3), len, val); - return val; -} - -static void elroy_config_data_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - PCIHostState *s = opaque; - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); - trace_elroy_pci_config_data_write(s->config_reg | (addr & 3), len, val); -} - -static const MemoryRegionOps elroy_config_data_ops = { - .read = elroy_config_data_read, - .write = elroy_config_data_write, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - static uint64_t elroy_config_addr_read(void *opaque, hwaddr addr, unsigned len) { ElroyState *s = opaque; @@ -424,6 +398,12 @@ static void elroy_reset(DeviceState *dev) } } +static void elroy_pcihost_instance_init(Object *obj) +{ + object_property_set_bool(obj, "config-reg-check-high-bit", false, + &error_fatal); +} + static void elroy_pcihost_realize(DeviceState *dev, Error **errp) { ElroyState *s = ELROY_PCI_HOST_BRIDGE(dev); @@ -440,7 +420,7 @@ static void elroy_pcihost_realize(DeviceState *dev, Error **errp) &elroy_config_addr_ops, dev, "pci-conf-idx", 8); memory_region_init_io(&phb->data_mem, obj, - &elroy_config_data_ops, dev, + &pci_host_data_le_ops, dev, "pci-conf-data", 8); memory_region_add_subregion(&s->this_mem, 0x40, &phb->conf_mem); @@ -497,6 +477,7 @@ static const TypeInfo elroy_pcihost_info = { .name = TYPE_ELROY_PCI_HOST_BRIDGE, .parent = TYPE_PCI_HOST_BRIDGE, .instance_size = sizeof(ElroyState), + .instance_init = elroy_pcihost_instance_init, .class_init = elroy_pcihost_class_init, }; diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index a6fd88c2c46..792ab25729b 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -76,7 +76,5 @@ astro_chip_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d astro_chip_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 elroy_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 elroy_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 -elroy_pci_config_data_read(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 -elroy_pci_config_data_write(uint64_t addr, int size, uint64_t val) "addr 0x%"PRIx64" size %d val 0x%"PRIx64 iosapic_reg_write(uint64_t reg_select, int size, uint64_t val) "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64 iosapic_reg_read(uint64_t reg_select, int size, uint64_t val) "reg_select 0x%"PRIx64" size %d val 0x%"PRIx64 -- 2.51.0