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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952df5c9sm14318157f8f.41.2025.10.27.06.32.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 27 Oct 2025 06:32:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , "Michael S. Tsirkin" , Richard Henderson , Marcel Apfelbaum , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 4/4] hw/pci-host/sabre: Re-use generic pci_host_data_le_ops MemoryRegionOps Date: Mon, 27 Oct 2025 14:30:37 +0100 Message-ID: <20251027133037.70487-5-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027133037.70487-1-philmd@linaro.org> References: <20251027133037.70487-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Avoid duplicating code, re-use the generic generic pci_host_data_le_ops MemoryRegionOps. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/sabre.c | 34 +++------------------------------- hw/pci-host/trace-events | 2 -- 2 files changed, 3 insertions(+), 33 deletions(-) diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index f95e5db583a..cc7229025f6 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -246,28 +246,6 @@ static const MemoryRegionOps sabre_config_ops = { .endianness = DEVICE_BIG_ENDIAN, }; -static void sabre_pci_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - SabreState *s = opaque; - PCIHostState *phb = PCI_HOST_BRIDGE(s); - - trace_sabre_pci_config_write(addr, val); - pci_data_write(phb->bus, addr, val, size); -} - -static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, - unsigned size) -{ - uint32_t ret; - SabreState *s = opaque; - PCIHostState *phb = PCI_HOST_BRIDGE(s); - - ret = pci_data_read(phb->bus, addr, size); - trace_sabre_pci_config_read(addr, ret); - return ret; -} - /* The sabre host has an IRQ line for each IRQ line of each slot. */ static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) { @@ -361,12 +339,6 @@ static void sabre_reset(DeviceState *d) pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); } -static const MemoryRegionOps pci_config_ops = { - .read = sabre_pci_config_read, - .write = sabre_pci_config_write, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - static void sabre_realize(DeviceState *dev, Error **errp) { SabreState *s = SABRE(dev); @@ -430,12 +402,12 @@ static void sabre_init(Object *obj) /* sabre_config */ memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, - "sabre-config", 0x10000); + "pci-conf-idx", 0x10000); /* at region 0 */ sysbus_init_mmio(sbd, &s->sabre_config); - memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, - "sabre-pci-config", 0x1000000); + memory_region_init_io(&s->pci_config, OBJECT(s), &pci_host_data_le_ops, s, + "pci-data-idx", 0x1000000); /* at region 1 */ sysbus_init_mmio(sbd, &s->pci_config); diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events index 792ab25729b..20c3cae47a2 100644 --- a/hw/pci-host/trace-events +++ b/hw/pci-host/trace-events @@ -35,8 +35,6 @@ sabre_set_request(int irq_num) "request irq %d" sabre_clear_request(int irq_num) "clear request irq %d" sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 -sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 -sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d" sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d" -- 2.51.0