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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952db9d1sm15064456f8f.35.2025.10.27.09.53.37 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 27 Oct 2025 09:53:38 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Richard Henderson , Marcel Apfelbaum , Mark Cave-Ayland , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/7] hw/pci/pci_host: Add 'config-reg-check-high-bit' property Date: Mon, 27 Oct 2025 17:52:57 +0100 Message-ID: <20251027165304.98296-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251027165304.98296-1-philmd@linaro.org> References: <20251027165304.98296-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In order to have more PCI host bridges to re-use the generic pci_host_data_le_ops MemoryRegionOps, add the 'config-reg-check-high-bit' property (%true by default). Signed-off-by: Philippe Mathieu-Daudé --- include/hw/pci/pci_host.h | 1 + hw/pci/pci_host.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index 954dd446fa4..c04a567ec57 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -43,6 +43,7 @@ struct PCIHostState { MemoryRegion data_mem; MemoryRegion mmcfg; uint32_t config_reg; + bool config_reg_check_high_bit; bool mig_enabled; PCIBus *bus; bool bypass_iommu; diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index b5c624e12e8..d6db365e327 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -184,8 +184,10 @@ static void pci_host_data_write(void *opaque, hwaddr addr, { PCIHostState *s = opaque; - if (s->config_reg & (1u << 31)) - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); + if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31))) { + return; + } + pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); } static uint64_t pci_host_data_read(void *opaque, @@ -193,7 +195,7 @@ static uint64_t pci_host_data_read(void *opaque, { PCIHostState *s = opaque; - if (!(s->config_reg & (1U << 31))) { + if (s->config_reg_check_high_bit && !(s->config_reg & (1U << 31))) { return 0xffffffff; } return pci_data_read(s->bus, s->config_reg | (addr & 3), len); @@ -235,6 +237,8 @@ const VMStateDescription vmstate_pcihost = { }; static const Property pci_host_properties_common[] = { + DEFINE_PROP_BOOL("config-reg-check-high-bit", PCIHostState, + config_reg_check_high_bit, true), DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState, mig_enabled, true), DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, false), -- 2.51.0