From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, philmd@linaro.org,
alistair.francis@wdc.com, palmer@dabbelt.com,
Anton Johansson <anjo@rev.ng>
Subject: [PATCH v4 02/33] target/riscv: Fix size of mhartid
Date: Mon, 27 Oct 2025 19:17:59 +0100 [thread overview]
Message-ID: <20251027181831.27016-3-anjo@rev.ng> (raw)
In-Reply-To: <20251027181831.27016-1-anjo@rev.ng>
and update formatting in log.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu_helper.c | 2 +-
target/riscv/machine.c | 2 +-
target/riscv/tcg/tcg-cpu.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 7ffc4dac26..adeb36abc2 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -280,7 +280,7 @@ struct CPUArchState {
target_ulong geilen;
uint64_t resetvec;
- target_ulong mhartid;
+ uint64_t mhartid;
/*
* For RV32 this is 32-bit mstatus and 32-bit mstatush.
* For RV64 this is a 64-bit mstatus.
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 360db133e2..1f791e4de3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -2277,7 +2277,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
riscv_cpu_get_trap_name(cause, async));
qemu_log_mask(CPU_LOG_INT,
- "%s: hart:"TARGET_FMT_ld", async:%d, cause:"TARGET_FMT_lx", "
+ "%s: hart:%"PRIu64", async:%d, cause:"TARGET_FMT_lx", "
"epc:0x"TARGET_FMT_lx", tval:0x"TARGET_FMT_lx", desc=%s\n",
__func__, env->mhartid, async, cause, env->pc, tval,
riscv_cpu_get_trap_name(cause, async));
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index f6ca017211..ab0bc32e1f 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -450,7 +450,7 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINTTL(env.priv, RISCVCPU),
VMSTATE_BOOL(env.virt_enabled, RISCVCPU),
VMSTATE_UINT64(env.resetvec, RISCVCPU),
- VMSTATE_UINTTL(env.mhartid, RISCVCPU),
+ VMSTATE_UINT64(env.mhartid, RISCVCPU),
VMSTATE_UINT64(env.mstatus, RISCVCPU),
VMSTATE_UINT64(env.mip, RISCVCPU),
VMSTATE_UINT64(env.miclaim, RISCVCPU),
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index d3968251fa..850a383702 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -489,7 +489,7 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
continue;
}
#ifndef CONFIG_USER_ONLY
- warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
+ warn_report("disabling %s extension for hart 0x%" PRIx64
" because privilege spec version does not match",
edata->name, env->mhartid);
#else
--
2.51.0
next prev parent reply other threads:[~2025-10-27 18:17 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 18:17 [PATCH v4 00/33] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-27 18:17 ` [PATCH v4 01/33] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-27 18:17 ` Anton Johansson via [this message]
2025-10-27 18:18 ` [PATCH v4 03/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-31 1:32 ` Alistair Francis
2025-10-31 13:05 ` Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 04/33] target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 05/33] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-28 8:14 ` Pierrick Bouvier
2025-10-27 18:18 ` [PATCH v4 06/33] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 07/33] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 09/33] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-28 8:15 ` Pierrick Bouvier
2025-10-27 18:18 ` [PATCH v4 10/33] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-31 1:56 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 11/33] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 12/33] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 13/33] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 14/33] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 15/33] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 16/33] target/riscv: Fix size of retxh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 17/33] target/riscv: Fix size of ssp Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 18/33] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-31 1:57 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 19/33] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 20/33] target/riscv: Fix size of priv Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 21/33] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 22/33] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-31 1:59 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 23/33] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-31 2:51 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 24/33] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-31 2:52 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 25/33] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 26/33] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-31 2:53 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-31 2:53 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 28/33] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-31 2:54 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 29/33] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-31 2:55 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 30/33] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 31/33] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 32/33] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 33/33] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
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