From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, philmd@linaro.org,
alistair.francis@wdc.com, palmer@dabbelt.com,
Anton Johansson <anjo@rev.ng>
Subject: [PATCH v4 03/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val()
Date: Mon, 27 Oct 2025 19:18:00 +0100 [thread overview]
Message-ID: <20251027181831.27016-4-anjo@rev.ng> (raw)
In-Reply-To: <20251027181831.27016-1-anjo@rev.ng>
From my understanding the upper_half argument only indicates whether the
upper or lower 32 bits should be returned, and upper_half will only ever
be set when MXLEN == 32. However, the function also uses upper_half to
determine whether the inhibit flags are located in mcyclecfgh or
mcyclecfg, but this misses the case where MXLEN == 32, upper_half == false
for TARGET_RISCV32 where we would also need to read the upper half field.
Minor simplifications are also made along with some formatting fixes.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
target/riscv/csr.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 5c91658c3d..657179a983 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -17,6 +17,7 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include "cpu_bits.h"
#include "qemu/osdep.h"
#include "qemu/log.h"
#include "qemu/timer.h"
@@ -1243,18 +1244,21 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
int inst = riscv_pmu_ctr_monitor_instructions(env, counter_idx);
uint64_t *counter_arr_virt = env->pmu_fixed_ctrs[inst].counter_virt;
uint64_t *counter_arr = env->pmu_fixed_ctrs[inst].counter;
- target_ulong result = 0;
uint64_t curr_val = 0;
uint64_t cfg_val = 0;
+ bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
+
+ /* Ensure upper_half is only set for MXL_RV32 */
+ g_assert(rv32 || !upper_half);
if (counter_idx == 0) {
- cfg_val = upper_half ? ((uint64_t)env->mcyclecfgh << 32) :
+ cfg_val = rv32 ? ((uint64_t)env->mcyclecfgh << 32) :
env->mcyclecfg;
} else if (counter_idx == 2) {
- cfg_val = upper_half ? ((uint64_t)env->minstretcfgh << 32) :
+ cfg_val = rv32 ? ((uint64_t)env->minstretcfgh << 32) :
env->minstretcfg;
} else {
- cfg_val = upper_half ?
+ cfg_val = rv32 ?
((uint64_t)env->mhpmeventh_val[counter_idx] << 32) :
env->mhpmevent_val[counter_idx];
cfg_val &= MHPMEVENT_FILTER_MASK;
@@ -1262,7 +1266,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
if (!cfg_val) {
if (icount_enabled()) {
- curr_val = inst ? icount_get_raw() : icount_get();
+ curr_val = inst ? icount_get_raw() : icount_get();
} else {
curr_val = cpu_get_host_ticks();
}
@@ -1294,13 +1298,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
}
done:
- if (riscv_cpu_mxl(env) == MXL_RV32) {
- result = upper_half ? curr_val >> 32 : curr_val;
- } else {
- result = curr_val;
- }
-
- return result;
+ return upper_half ? curr_val >> 32 : curr_val;
}
static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong val,
--
2.51.0
next prev parent reply other threads:[~2025-10-27 18:18 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 18:17 [PATCH v4 00/33] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-27 18:17 ` [PATCH v4 01/33] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-27 18:17 ` [PATCH v4 02/33] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-27 18:18 ` Anton Johansson via [this message]
2025-10-31 1:32 ` [PATCH v4 03/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Alistair Francis
2025-10-31 13:05 ` Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 04/33] target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 05/33] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-28 8:14 ` Pierrick Bouvier
2025-10-27 18:18 ` [PATCH v4 06/33] target/riscv: Combine mcyclecfg and mcyclecfgh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 07/33] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 09/33] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-28 8:15 ` Pierrick Bouvier
2025-10-27 18:18 ` [PATCH v4 10/33] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-31 1:56 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 11/33] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 12/33] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 13/33] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 14/33] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 15/33] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 16/33] target/riscv: Fix size of retxh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 17/33] target/riscv: Fix size of ssp Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 18/33] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-31 1:57 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 19/33] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 20/33] target/riscv: Fix size of priv Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 21/33] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 22/33] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-31 1:59 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 23/33] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-31 2:51 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 24/33] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-31 2:52 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 25/33] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 26/33] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-31 2:53 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-31 2:53 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 28/33] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-31 2:54 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 29/33] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-31 2:55 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 30/33] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 31/33] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 32/33] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 33/33] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
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