From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, philmd@linaro.org,
alistair.francis@wdc.com, palmer@dabbelt.com,
Anton Johansson <anjo@rev.ng>
Subject: [PATCH v4 06/33] target/riscv: Combine mcyclecfg and mcyclecfgh
Date: Mon, 27 Oct 2025 19:18:03 +0100 [thread overview]
Message-ID: <20251027181831.27016-7-anjo@rev.ng> (raw)
In-Reply-To: <20251027181831.27016-1-anjo@rev.ng>
According to version 20250508 of the privileged specification, mcyclecfg
is a 64-bit register and mcyclecfgh refers to the top 32 bits of this
register when XLEN == 32. No real advantage is gained by keeping
them separate, and combining them allows for slight simplification.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
target/riscv/cpu.h | 3 +--
target/riscv/csr.c | 28 +++++++++++++++++-----------
2 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0791959fcd..e15439dab7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -420,8 +420,7 @@ struct CPUArchState {
uint32_t mcountinhibit;
/* PMU cycle & instret privilege mode filtering */
- target_ulong mcyclecfg;
- target_ulong mcyclecfgh;
+ uint64_t mcyclecfg;
target_ulong minstretcfg;
target_ulong minstretcfgh;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 55110b4b66..ddd80ab68d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1062,7 +1062,8 @@ static RISCVException read_hpmcounterh(CPURISCVState *env, int csrno,
static RISCVException read_mcyclecfg(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->mcyclecfg;
+ bool rv32 = riscv_cpu_mxl(env) == MXL_RV32;
+ *val = extract64(env->mcyclecfg, 0, rv32 ? 32 : 64);
return RISCV_EXCP_NONE;
}
@@ -1072,7 +1073,7 @@ static RISCVException write_mcyclecfg(CPURISCVState *env, int csrno,
uint64_t inh_avail_mask;
if (riscv_cpu_mxl(env) == MXL_RV32) {
- env->mcyclecfg = val;
+ env->mcyclecfg = deposit64(env->mcyclecfg, 0, 32, val);
} else {
/* Set xINH fields if priv mode supported */
inh_avail_mask = ~MHPMEVENT_FILTER_MASK | MCYCLECFG_BIT_MINH;
@@ -1091,7 +1092,7 @@ static RISCVException write_mcyclecfg(CPURISCVState *env, int csrno,
static RISCVException read_mcyclecfgh(CPURISCVState *env, int csrno,
target_ulong *val)
{
- *val = env->mcyclecfgh;
+ *val = extract64(env->mcyclecfg, 32, 32);
return RISCV_EXCP_NONE;
}
@@ -1109,7 +1110,7 @@ static RISCVException write_mcyclecfgh(CPURISCVState *env, int csrno,
inh_avail_mask |= (riscv_has_ext(env, RVH) &&
riscv_has_ext(env, RVS)) ? MCYCLECFGH_BIT_VSINH : 0;
- env->mcyclecfgh = val & inh_avail_mask;
+ env->mcyclecfg = deposit64(env->mcyclecfg, 32, 32, val & inh_avail_mask);
return RISCV_EXCP_NONE;
}
@@ -1248,8 +1249,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
g_assert(rv32 || !upper_half);
if (counter_idx == 0) {
- cfg_val = rv32 ? ((uint64_t)env->mcyclecfgh << 32) :
- env->mcyclecfg;
+ cfg_val = env->mcyclecfg;
} else if (counter_idx == 2) {
cfg_val = rv32 ? ((uint64_t)env->minstretcfgh << 32) :
env->minstretcfg;
@@ -1523,8 +1523,12 @@ static int rmw_cd_mhpmeventh(CPURISCVState *env, int evt_index,
}
static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val,
- target_ulong new_val, target_ulong wr_mask)
+ target_ulong new_val, uint64_t wr_mask)
{
+ /*
+ * wr_mask is 64-bit so upper 32 bits of mcyclecfg and minstretcfg
+ * are retained.
+ */
switch (cfg_index) {
case 0: /* CYCLECFG */
if (wr_mask) {
@@ -1550,8 +1554,9 @@ static int rmw_cd_ctr_cfg(CPURISCVState *env, int cfg_index, target_ulong *val,
}
static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong *val,
- target_ulong new_val, target_ulong wr_mask)
+ target_ulong new_val, target_ulong wr_mask)
{
+ uint64_t cfgh;
if (riscv_cpu_mxl(env) != MXL_RV32) {
return RISCV_EXCP_ILLEGAL_INST;
@@ -1559,12 +1564,13 @@ static int rmw_cd_ctr_cfgh(CPURISCVState *env, int cfg_index, target_ulong *val,
switch (cfg_index) {
case 0: /* CYCLECFGH */
+ cfgh = extract64(env->mcyclecfg, 32, 32);
if (wr_mask) {
wr_mask &= ~MCYCLECFGH_BIT_MINH;
- env->mcyclecfgh = (new_val & wr_mask) |
- (env->mcyclecfgh & ~wr_mask);
+ cfgh = (new_val & wr_mask) | (cfgh & ~wr_mask);
+ env->mcyclecfg = deposit64(env->mcyclecfg, 32, 32, cfgh);
} else {
- *val = env->mcyclecfgh;
+ *val = cfgh;
}
break;
case 2: /* INSTRETCFGH */
--
2.51.0
next prev parent reply other threads:[~2025-10-27 18:18 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-27 18:17 [PATCH v4 00/33] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-10-27 18:17 ` [PATCH v4 01/33] target/riscv: Fix size of trivial CPUArchState fields Anton Johansson via
2025-10-27 18:17 ` [PATCH v4 02/33] target/riscv: Fix size of mhartid Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 03/33] target/riscv: Bugfix riscv_pmu_ctr_get_fixed_counters_val() Anton Johansson via
2025-10-31 1:32 ` Alistair Francis
2025-10-31 13:05 ` Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 04/33] target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 05/33] target/riscv: Combine mhpmevent and mhpmeventh Anton Johansson via
2025-10-28 8:14 ` Pierrick Bouvier
2025-10-27 18:18 ` Anton Johansson via [this message]
2025-10-27 18:18 ` [PATCH v4 07/33] target/riscv: Combine minstretcfg and minstretcfgh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 08/33] target/riscv: Combine mhpmcounter and mhpmcounterh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 09/33] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-10-28 8:15 ` Pierrick Bouvier
2025-10-27 18:18 ` [PATCH v4 10/33] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-10-31 1:56 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 11/33] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 12/33] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 13/33] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 14/33] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 15/33] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 16/33] target/riscv: Fix size of retxh Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 17/33] target/riscv: Fix size of ssp Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 18/33] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-10-31 1:57 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 19/33] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 20/33] target/riscv: Fix size of priv Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 21/33] target/riscv: Fix size of gei fields Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 22/33] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-10-31 1:59 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 23/33] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-10-31 2:51 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 24/33] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-10-31 2:52 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 25/33] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 26/33] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-10-31 2:53 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 27/33] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-10-31 2:53 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 28/33] target/riscv: Fix size of trigger data Anton Johansson via
2025-10-31 2:54 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 29/33] target/riscv: Fix size of mseccfg Anton Johansson via
2025-10-31 2:55 ` Alistair Francis
2025-10-27 18:18 ` [PATCH v4 30/33] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 31/33] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 32/33] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-10-27 18:18 ` [PATCH v4 33/33] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
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