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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-429952df3c7sm18048239f8f.40.2025.10.27.23.16.54 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 27 Oct 2025 23:16:55 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mads Ynddal , Cameron Esfahani , qemu-arm@nongnu.org, Roman Bolshakov , Akihiko Odaki , Phil Dennis-Jordan , Mohamed Mediouni , Peter Collingbourne , Peter Maydell , Alexander Graf , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 48/59] target/arm/hvf: Really set Generic Timer counter frequency Date: Tue, 28 Oct 2025 06:42:24 +0100 Message-ID: <20251028054238.14949-49-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251028054238.14949-1-philmd@linaro.org> References: <20251028054238.14949-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Setting ARMCPU::gt_cntfrq_hz in hvf_arch_init_vcpu() is not correct because the timers have already be initialized with the default frequency. Set it earlier in the AccelOpsClass::cpu_target_realize() handler instead, and assert the value is correct when reaching hvf_arch_init_vcpu(). Fixes: a1477da3dde ("hvf: Add Apple Silicon support") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/hvf/hvf.c | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b053bdd7cf2..0788b20cc05 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -897,6 +897,13 @@ cleanup: return ret; } +static uint64_t get_cntfrq_el0(void) +{ + uint64_t freq_hz = 0; + asm volatile("mrs %0, cntfrq_el0" : "=r"(freq_hz)); + return freq_hz; +} + int hvf_arch_init_vcpu(CPUState *cpu) { ARMCPU *arm_cpu = ARM_CPU(cpu); @@ -908,7 +915,9 @@ int hvf_arch_init_vcpu(CPUState *cpu) int i; env->aarch64 = true; - asm volatile("mrs %0, cntfrq_el0" : "=r"(arm_cpu->gt_cntfrq_hz)); + + /* system count frequency sanity check */ + assert(arm_cpu->gt_cntfrq_hz == get_cntfrq_el0()); /* Allocate enough space for our sysreg sync */ arm_cpu->cpreg_indexes = g_renew(uint64_t, arm_cpu->cpreg_indexes, @@ -974,6 +983,15 @@ int hvf_arch_init_vcpu(CPUState *cpu) bool hvf_arch_cpu_realize(CPUState *cs, Error **errp) { + ARMCPU *cpu = ARM_CPU(cs); + + /* + * We must set the counter frequency HVF will be using + * early, before arm_cpu_realizefn initializes the timers + * with it. + */ + cpu->gt_cntfrq_hz = get_cntfrq_el0(); + return true; } -- 2.51.0