From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Mads Ynddal" <mads@ynddal.dk>,
"Cameron Esfahani" <dirty@apple.com>,
qemu-arm@nongnu.org, "Roman Bolshakov" <rbolshakov@ddn.com>,
"Akihiko Odaki" <odaki@rsg.ci.i.u-tokyo.ac.jp>,
"Phil Dennis-Jordan" <phil@philjordan.eu>,
"Mohamed Mediouni" <mohamed@unpredictable.fr>,
"Peter Collingbourne" <pcc@google.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Alexander Graf" <agraf@csgraf.de>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@linaro.org>
Subject: [PATCH v3 59/59] target/arm/hvf: Emulate PhysTimer registers
Date: Tue, 28 Oct 2025 06:42:35 +0100 [thread overview]
Message-ID: <20251028054238.14949-60-philmd@linaro.org> (raw)
In-Reply-To: <20251028054238.14949-1-philmd@linaro.org>
Emulate PhysTimer dispatching to TCG, like we do with GIC registers.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
TODO: audit it is safe
---
target/arm/hvf/hvf.c | 30 +++++++++++++++++++-----------
1 file changed, 19 insertions(+), 11 deletions(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 113f1415011..a7b5e4711b0 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -189,6 +189,7 @@ void hvf_arm_init_debug(void)
#define SYSREG_LORC_EL1 SYSREG(3, 0, 10, 4, 3)
#define SYSREG_CNTPCT_EL0 SYSREG(3, 3, 14, 0, 1)
#define SYSREG_CNTP_CTL_EL0 SYSREG(3, 3, 14, 2, 1)
+#define SYSREG_CNTP_CVAL_EL0 SYSREG(3, 3, 14, 2, 2)
#define SYSREG_PMCR_EL0 SYSREG(3, 3, 9, 12, 0)
#define SYSREG_PMUSERENR_EL0 SYSREG(3, 3, 9, 14, 0)
#define SYSREG_PMCNTENSET_EL0 SYSREG(3, 3, 9, 12, 1)
@@ -201,6 +202,8 @@ void hvf_arm_init_debug(void)
#define SYSREG_PMCEID1_EL0 SYSREG(3, 3, 9, 12, 7)
#define SYSREG_PMCCNTR_EL0 SYSREG(3, 3, 9, 13, 0)
+#define SYSREG_CNTP_TVAL_EL0 SYSREG(3, 3, 14, 2, 0)
+#define SYSREG_CNTP_CVAL_EL0 SYSREG(3, 3, 14, 2, 2)
#define SYSREG_CNTV_CTL_EL0 SYSREG(3, 3, 14, 3, 1)
#define SYSREG_CNTV_CVAL_EL0 SYSREG(3, 3, 14, 3, 2)
#define SYSREG_PMCCFILTR_EL0 SYSREG(3, 3, 14, 15, 7)
@@ -1249,16 +1252,20 @@ static int hvf_sysreg_read(CPUState *cpu, uint32_t reg, uint64_t *val)
}
switch (reg) {
- case SYSREG_CNTPCT_EL0:
- *val = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) /
- gt_cntfrq_period_ns(arm_cpu);
- return 0;
case SYSREG_OSLSR_EL1:
*val = env->cp15.oslsr_el1;
return 0;
case SYSREG_OSDLR_EL1:
/* Dummy register */
return 0;
+ case SYSREG_CNTP_CTL_EL0:
+ case SYSREG_CNTP_TVAL_EL0:
+ case SYSREG_CNTPCT_EL0:
+ /* Call the TCG sysreg handler. This is only safe for VTimer regs. */
+ if (hvf_sysreg_read_cp(cpu, "VTimer", reg, val)) {
+ return 0;
+ }
+ break;
case SYSREG_ICC_AP0R0_EL1:
case SYSREG_ICC_AP0R1_EL1:
case SYSREG_ICC_AP0R2_EL1:
@@ -1571,19 +1578,20 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t reg, uint64_t val)
case SYSREG_OSLAR_EL1:
env->cp15.oslsr_el1 = val & 1;
return 0;
- case SYSREG_CNTP_CTL_EL0:
- /*
- * Guests should not rely on the physical counter, but macOS emits
- * disable writes to it. Let it do so, but ignore the requests.
- */
- qemu_log_mask(LOG_UNIMP, "Unsupported write to CNTP_CTL_EL0\n");
- return 0;
case SYSREG_OSDLR_EL1:
/* Dummy register */
return 0;
case SYSREG_LORC_EL1:
/* Dummy register */
return 0;
+ case SYSREG_CNTP_CTL_EL0:
+ case SYSREG_CNTP_CVAL_EL0:
+ case SYSREG_CNTP_TVAL_EL0:
+ /* Call the TCG sysreg handler. This is only safe for VTimer regs. */
+ if (hvf_sysreg_write_cp(cpu, "VTimer", reg, val)) {
+ return 0;
+ }
+ break;
case SYSREG_ICC_AP0R0_EL1:
case SYSREG_ICC_AP0R1_EL1:
case SYSREG_ICC_AP0R2_EL1:
--
2.51.0
next prev parent reply other threads:[~2025-10-28 6:25 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-28 5:41 [PATCH v3 00/59] target/arm/hvf: Consolidate Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 01/59] target/arm/hvf: Release memory allocated by hv_vcpu_config_create() Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 02/59] target/arm/hvf: Trace vCPU KICK events Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 03/59] target/arm/hvf: Check hv_vcpus_exit() returned value Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 04/59] target/arm/hvf: Check hv_vcpu_set_vtimer_mask() " Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 05/59] accel/hvf: Rename hvf_vcpu_exec() -> hvf_arch_vcpu_exec() Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 06/59] accel/hvf: Rename hvf_put|get_registers -> hvf_arch_put|get_registers Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 07/59] target/arm/hvf: Mention flush_cpu_state() must run on vCPU thread Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 08/59] accel/hvf: Mention hvf_arch_init_vcpu() " Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 09/59] target/arm/hvf: Mention hvf_sync_vtimer() " Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 10/59] target/arm/hvf: Mention hvf_arch_set_traps() " Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 11/59] accel/hvf: Mention hvf_arch_update_guest_debug() must run on vCPU Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 12/59] target/arm/hvf: Mention hvf_inject_interrupts() must run on vCPU thread Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 13/59] accel/hvf: Implement hvf_arch_vcpu_destroy() Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 14/59] target/arm/hvf: Hardcode Apple MIDR Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 15/59] target/arm/hvf: Simplify hvf_arm_get_host_cpu_features() Philippe Mathieu-Daudé
2025-10-28 11:16 ` Peter Maydell
2025-10-28 11:33 ` Richard Henderson
2025-10-28 5:41 ` [PATCH v3 16/59] target/arm/hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 17/59] target/arm/hvf: Factor hvf_handle_exception() out Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 18/59] target/i386/hvf: Factor hvf_handle_vmexit() out Philippe Mathieu-Daudé
2025-10-28 11:18 ` Peter Maydell
2025-10-28 5:41 ` [PATCH v3 19/59] target/arm/hvf: " Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 20/59] target/arm/hvf: Keep calling hv_vcpu_run() in loop Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 21/59] cpus: Trace cpu_exec_start() and cpu_exec_end() calls Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 22/59] accel/hvf: Guard hv_vcpu_run() between cpu_exec_start/end() calls Philippe Mathieu-Daudé
2025-10-28 5:41 ` [PATCH v3 23/59] target/arm: Call aarch64_add_pauth_properties() once in host_initfn() Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 24/59] accel/hvf: Restrict ARM specific fields of AccelCPUState Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 25/59] target/arm: Rename init_cpreg_list() -> arm_init_cpreg_list() Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 26/59] target/arm/hvf: Rename 'vgic' -> 'emu_reginfo' in trace events Philippe Mathieu-Daudé
2025-10-28 11:23 ` Peter Maydell
2025-10-28 5:42 ` [PATCH v3 27/59] target/arm: Re-use arm_is_psci_call() in HVF Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 28/59] target/arm: Share ARM_PSCI_CALL trace event between TCG and HVF Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 29/59] target/arm/hvf/hvf: Document $pc adjustment in HVF & SMC Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 30/59] accel/hvf: Trace prefetch abort Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 31/59] accel/hvf: Create hvf_protect_clean_range, hvf_unprotect_dirty_range Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 32/59] accel/hvf: Enforce host alignment in hv_vm_protect() Philippe Mathieu-Daudé
2025-10-28 11:26 ` Peter Maydell
2025-10-28 11:44 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 33/59] target/i386/hvf: Use host page alignment in ept_emulation_fault() Philippe Mathieu-Daudé
2025-10-28 11:28 ` Peter Maydell
2025-11-03 10:00 ` Philippe Mathieu-Daudé
2025-10-28 11:47 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 34/59] target/i386/hvf: Use hvf_unprotect_page Philippe Mathieu-Daudé
2025-10-28 11:29 ` Peter Maydell
2025-10-28 5:42 ` [PATCH v3 35/59] target/i386/hvf: Use address_space_translate in ept_emulation_fault Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 36/59] accel/hvf: Simplify hvf_log_* Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 37/59] accel/hvf: Move hvf_log_sync to hvf_log_clear Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 38/59] accel/hvf: Simplify hvf_set_phys_mem Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 39/59] accel/hvf: Drop hvf_slot and hvf_find_overlap_slot Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 40/59] accel/hvf: Remove mac_slots Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 41/59] target/arm/hvf: Implement dirty page tracking Philippe Mathieu-Daudé
2025-10-28 11:58 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 42/59] accel/hvf: Skip WFI if CPU has work to do Philippe Mathieu-Daudé
2025-10-28 11:51 ` Alex Bennée
2025-10-28 11:59 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 43/59] accel/hvf: Implement WFI without using pselect() Philippe Mathieu-Daudé
2025-10-28 12:01 ` Richard Henderson
2025-11-03 10:01 ` Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 44/59] accel/hvf: Have PSCI CPU_SUSPEND halt the vCPU Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 45/59] accel: Introduce AccelOpsClass::cpu_target_realize() hook Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 46/59] accel/hvf: Add hvf_arch_cpu_realize() stubs Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 47/59] target/arm: Create GTimers *after* features finalized / accel realized Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 48/59] target/arm/hvf: Really set Generic Timer counter frequency Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 49/59] target/arm: Only allow disabling NEON when using TCG Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 50/59] target/arm/hvf: Do not abort in hvf_arm_get_*_ipa_bit_size() Philippe Mathieu-Daudé
2025-10-28 12:06 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 51/59] hw/arm/virt: Warn when HVF doesn't report IPA bit length Philippe Mathieu-Daudé
2025-10-28 12:07 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 52/59] accel/hvf: Introduce hvf_arch_cpu_synchronize_[pre/post]exec() hooks Philippe Mathieu-Daudé
2025-10-28 12:08 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 53/59] target/i386/hvf: Flush vCPU registers once before vcpu_exec() loop Philippe Mathieu-Daudé
2025-10-28 12:09 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 54/59] target/arm/hvf: " Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 55/59] accel/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0 Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 56/59] target/arm: Better describe PMU depends on TCG or HVF Philippe Mathieu-Daudé
2025-10-28 12:29 ` Richard Henderson
2025-10-28 5:42 ` [PATCH v3 57/59] target/arm/hvf: Emulate PMU registers Philippe Mathieu-Daudé
2025-10-28 5:42 ` [PATCH v3 58/59] target/arm/hvf: Emulate Monitor Debug registers Philippe Mathieu-Daudé
2025-10-28 5:42 ` Philippe Mathieu-Daudé [this message]
2025-10-28 13:10 ` [PATCH v3 00/59] target/arm/hvf: Consolidate Peter Maydell
2025-10-28 15:41 ` Philippe Mathieu-Daudé
2025-10-28 15:45 ` Peter Maydell
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