qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Anton Johansson" <anjo@rev.ng>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Weiwei Li" <liwei1518@gmail.com>,
	"Daniel Henrique Barboza" <dbarboza@ventanamicro.com>,
	"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
	qemu-riscv@nongnu.org
Subject: [PULL 22/23] hw/riscv: Use generic hwaddr for firmware addresses
Date: Tue, 28 Oct 2025 08:48:58 +0100	[thread overview]
Message-ID: <20251028074901.22062-23-philmd@linaro.org> (raw)
In-Reply-To: <20251028074901.22062-1-philmd@linaro.org>

From: Anton Johansson <anjo@rev.ng>

Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-ID: <20251027-feature-single-binary-hw-v1-v2-1-44478d589ae9@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[PMD: Do not update riscv_load_kernel()]
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 include/hw/riscv/boot.h    | 18 +++++++++---------
 hw/riscv/boot.c            | 20 ++++++++++----------
 hw/riscv/microchip_pfsoc.c |  2 +-
 hw/riscv/sifive_u.c        |  2 +-
 hw/riscv/spike.c           |  4 ++--
 hw/riscv/virt.c            |  2 +-
 6 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h
index 7d59b2e6c63..51b0e13bd3e 100644
--- a/include/hw/riscv/boot.h
+++ b/include/hw/riscv/boot.h
@@ -43,18 +43,18 @@ bool riscv_is_32bit(RISCVHartArrayState *harts);
 char *riscv_plic_hart_config_string(int hart_count);
 
 void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts);
-target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
-                                          target_ulong firmware_end_addr);
-target_ulong riscv_find_and_load_firmware(MachineState *machine,
-                                          const char *default_machine_firmware,
-                                          hwaddr *firmware_load_addr,
-                                          symbol_fn_t sym_cb);
+hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
+                                    hwaddr firmware_end_addr);
+hwaddr riscv_find_and_load_firmware(MachineState *machine,
+                                    const char *default_machine_firmware,
+                                    hwaddr *firmware_load_addr,
+                                    symbol_fn_t sym_cb);
 const char *riscv_default_firmware_name(RISCVHartArrayState *harts);
 char *riscv_find_firmware(const char *firmware_filename,
                           const char *default_machine_firmware);
-target_ulong riscv_load_firmware(const char *firmware_filename,
-                                 hwaddr *firmware_load_addr,
-                                 symbol_fn_t sym_cb);
+hwaddr riscv_load_firmware(const char *firmware_filename,
+                           hwaddr *firmware_load_addr,
+                           symbol_fn_t sym_cb);
 void riscv_load_kernel(MachineState *machine,
                        RISCVBootInfo *info,
                        target_ulong kernel_start_addr,
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index f38078c8c22..9510fca939b 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -74,8 +74,8 @@ void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts)
     info->is_32bit = riscv_is_32bit(harts);
 }
 
-target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info,
-                                          target_ulong firmware_end_addr) {
+hwaddr riscv_calc_kernel_start_addr(RISCVBootInfo *info,
+                                    hwaddr firmware_end_addr) {
     if (info->is_32bit) {
         return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB);
     } else {
@@ -133,13 +133,13 @@ char *riscv_find_firmware(const char *firmware_filename,
     return filename;
 }
 
-target_ulong riscv_find_and_load_firmware(MachineState *machine,
-                                          const char *default_machine_firmware,
-                                          hwaddr *firmware_load_addr,
-                                          symbol_fn_t sym_cb)
+hwaddr riscv_find_and_load_firmware(MachineState *machine,
+                                    const char *default_machine_firmware,
+                                    hwaddr *firmware_load_addr,
+                                    symbol_fn_t sym_cb)
 {
     char *firmware_filename;
-    target_ulong firmware_end_addr = *firmware_load_addr;
+    hwaddr firmware_end_addr = *firmware_load_addr;
 
     firmware_filename = riscv_find_firmware(machine->firmware,
                                             default_machine_firmware);
@@ -154,9 +154,9 @@ target_ulong riscv_find_and_load_firmware(MachineState *machine,
     return firmware_end_addr;
 }
 
-target_ulong riscv_load_firmware(const char *firmware_filename,
-                                 hwaddr *firmware_load_addr,
-                                 symbol_fn_t sym_cb)
+hwaddr riscv_load_firmware(const char *firmware_filename,
+                           hwaddr *firmware_load_addr,
+                           symbol_fn_t sym_cb)
 {
     uint64_t firmware_entry, firmware_end;
     ssize_t firmware_size;
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4c939d8e96c..a17f62cd082 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -521,7 +521,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine)
     uint64_t mem_low_size, mem_high_size;
     hwaddr firmware_load_addr;
     const char *firmware_name;
-    target_ulong firmware_end_addr, kernel_start_addr;
+    hwaddr firmware_end_addr, kernel_start_addr;
     uint64_t kernel_entry;
     uint64_t fdt_load_addr;
     DriveInfo *dinfo = drive_get(IF_SD, 0, 0);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3e1ed209ca9..a7492aa27a4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -515,7 +515,7 @@ static void sifive_u_machine_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
     hwaddr start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
-    target_ulong firmware_end_addr, kernel_start_addr;
+    hwaddr firmware_end_addr, kernel_start_addr;
     const char *firmware_name;
     uint32_t start_addr_hi32 = 0x00000000;
     uint32_t fdt_load_addr_hi32 = 0x00000000;
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 641aae8c019..b0bab3fe008 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -197,9 +197,9 @@ static void spike_board_init(MachineState *machine)
     SpikeState *s = SPIKE_MACHINE(machine);
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
-    target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base;
+    hwaddr firmware_end_addr = memmap[SPIKE_DRAM].base;
     hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base;
-    target_ulong kernel_start_addr;
+    hwaddr kernel_start_addr;
     char *firmware_name;
     uint64_t fdt_load_addr;
     uint64_t kernel_entry;
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 47e573f85ab..17909206c7e 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1434,7 +1434,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
                                      machine_done);
     MachineState *machine = MACHINE(s);
     hwaddr start_addr = s->memmap[VIRT_DRAM].base;
-    target_ulong firmware_end_addr, kernel_start_addr;
+    hwaddr firmware_end_addr, kernel_start_addr;
     const char *firmware_name = riscv_default_firmware_name(&s->soc[0]);
     uint64_t fdt_load_addr;
     uint64_t kernel_entry = 0;
-- 
2.51.0



  parent reply	other threads:[~2025-10-28  7:57 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-28  7:48 [PULL 00/23] Misc HW patches for 2025-10-28 Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 01/23] target/hppa: Set FPCR exception flag bits for non-trapped exceptions Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 02/23] qom: remove redundant typedef when use OBJECT_DECLARE_SIMPLE_TYPE Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 03/23] hw/net/virtio-net: make VirtIONet.vlans an array instead of a pointer Philippe Mathieu-Daudé
2025-12-09 12:15   ` Fiona Ebner
2025-12-09 20:07     ` Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 04/23] migration/vmstate: remove VMSTATE_BUFFER_POINTER_UNSAFE macro Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 05/23] hw/pci-host/raven: Simplify creating PCI facing part Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 06/23] hw/pci-host/raven: Simplify " Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 07/23] hw/pci-host/raven: Simplify host bridge type declaration Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 08/23] hw/pci-host/raven: Use DEFINE_TYPES macro Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 09/23] hw/pci-host/raven: Simplify PCI bus creation Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 10/23] hw/qdev: Have qdev_get_gpio_out_connector() take const DeviceState arg Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 11/23] hw/sysbus: Have various helpers take a const SysBusDevice argument Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 12/23] hw/uefi: Include missing 'system/memory.h' header Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 13/23] hw/int/loongarch: " Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 14/23] hw/core/loader: Use qemu_open() instead of open() in get_image_size() Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 15/23] hw/core/loader: capture Error from load_image_targphys Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 16/23] hw/core/loader: improve error handling in image loading functions Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 17/23] hw/core/loader: add check for zero size in load_image_targphys_as Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 18/23] hw/core/loader: Pass errp to load_image_targphys_as() Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 19/23] hw/ppc: Pass error_fatal to load_image_targphys() Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 20/23] nw/nvram/ds1225y: Fix nvram MemoryRegion owner Philippe Mathieu-Daudé
2025-10-28  7:48 ` [PULL 21/23] hw/i386/intel_iommu: Remove an unused state field Philippe Mathieu-Daudé
2025-10-28  7:48 ` Philippe Mathieu-Daudé [this message]
2025-10-28  7:48 ` [PULL 23/23] hw/riscv: Widen OpenSBI dynamic info struct Philippe Mathieu-Daudé
2025-10-28 12:12 ` [PULL 00/23] Misc HW patches for 2025-10-28 Richard Henderson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251028074901.22062-23-philmd@linaro.org \
    --to=philmd@linaro.org \
    --cc=alistair.francis@wdc.com \
    --cc=anjo@rev.ng \
    --cc=dbarboza@ventanamicro.com \
    --cc=liwei1518@gmail.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).