* [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability
@ 2025-10-29 4:36 Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 01/17] hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file " Jamin Lin via
` (16 more replies)
0 siblings, 17 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This series depends on the following patch series:
Split AST2500 SoC machines into separate source files for maintainability
https://patchwork.kernel.org/project/qemu-devel/cover/20251023100150.295370-1-jamin_lin@aspeedtech.com/
v1:
1. Split each Aspeed machine into its own source file for better
readability and maintainability:
- Quanta-Q71L
- Supermicro X11
- Palmetto
- Bletchley
- fby35 BMC
- Facebook Fuji
- QCOM Firework
- QCOM DC-SCM V1
- GB200NVL
- Rainier
- Catalina
- AST2600 EVB
- AST2700 EVB
- AST1030 EVB
2. Make aspeed_machine_ast2600_class_emmc_init() a shared API
for eMMC boot setup.
3. Promote connect_serial_hds_to_uarts() to a public machine API
for reuse across platforms.
v2:
1. Restore ASPEED_RAM_SIZE() macro
Jamin Lin (17):
hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file
for maintainability
hw/arm/aspeed: Split Supermicro X11 machine into a separate source
file for maintainability
hw/arm/aspeed: Split Palmetto machine into a separate source file for
maintainability
hw/arm/aspeed: Move ASPEED_RAM_SIZE() macro to common header for reuse
hw/arm/aspeed: Split Bletchley machine into a separate source file for
maintainability
hw/arm/aspeed: Split FBY35 BMC machine into a separate source file for
maintainability
hw/arm/aspeed: Split Fuji machine into a separate source file for
maintainability
hw/arm/aspeed: Split QCOM Firework machine into a separate source file
for maintainability
hw/arm/aspeed: Split QCOM DC-SCM V1 machine into a separate source
file for maintainability
hw/arm/aspeed: Make aspeed_machine_ast2600_class_emmc_init() a common
API for eMMC boot setup
hw/arm/aspeed: Split GB200NVL machine into a separate source file for
maintainability
hw/arm/aspeed: Split Rainier machine into a separate source file for
maintainability
hw/arm/aspeed: Split Catalina machine into a separate source file for
maintainability
hw/arm/aspeed: Split AST2600 EVB machine into a separate source file
for maintainability
hw/arm/aspeed: Split AST2700 EVB machine into a separate source file
for maintainability
hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine
API
hw/arm/aspeed: Split AST1030 EVB machine into a separate source file
for maintainability
hw/arm/aspeed_eeprom.h | 25 -
include/hw/arm/aspeed.h | 9 +
hw/arm/aspeed.c | 1144 +----------------
hw/arm/aspeed_ast10x0_evb.c | 107 ++
hw/arm/aspeed_ast2400_palmetto.c | 79 ++
hw/arm/aspeed_ast2400_quanta-q71l.c | 85 ++
hw/arm/aspeed_ast2400_supermicrox11.c | 80 ++
hw/arm/aspeed_ast2600_bletchley.c | 96 ++
hw/arm/aspeed_ast2600_catalina.c | 224 ++++
hw/arm/aspeed_ast2600_evb.c | 64 +
...aspeed_eeprom.c => aspeed_ast2600_fby35.c} | 165 ++-
hw/arm/aspeed_ast2600_fuji.c | 139 ++
hw/arm/aspeed_ast2600_gb200nvl.c | 110 ++
hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c | 54 +
hw/arm/aspeed_ast2600_qcom-firework.c | 90 ++
hw/arm/aspeed_ast2600_rainier.c | 197 +++
hw/arm/aspeed_ast27x0_evb.c | 86 ++
hw/arm/meson.build | 15 +-
18 files changed, 1533 insertions(+), 1236 deletions(-)
delete mode 100644 hw/arm/aspeed_eeprom.h
create mode 100644 hw/arm/aspeed_ast10x0_evb.c
create mode 100644 hw/arm/aspeed_ast2400_palmetto.c
create mode 100644 hw/arm/aspeed_ast2400_quanta-q71l.c
create mode 100644 hw/arm/aspeed_ast2400_supermicrox11.c
create mode 100644 hw/arm/aspeed_ast2600_bletchley.c
create mode 100644 hw/arm/aspeed_ast2600_catalina.c
create mode 100644 hw/arm/aspeed_ast2600_evb.c
rename hw/arm/{aspeed_eeprom.c => aspeed_ast2600_fby35.c} (51%)
create mode 100644 hw/arm/aspeed_ast2600_fuji.c
create mode 100644 hw/arm/aspeed_ast2600_gb200nvl.c
create mode 100644 hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c
create mode 100644 hw/arm/aspeed_ast2600_qcom-firework.c
create mode 100644 hw/arm/aspeed_ast2600_rainier.c
create mode 100644 hw/arm/aspeed_ast27x0_evb.c
--
2.43.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH v2 01/17] hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 02/17] hw/arm/aspeed: Split Supermicro X11 " Jamin Lin via
` (15 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Quanta-Q71L BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2400_quanta-q71l.c.
This refactor continues the modularization effort for Aspeed platform
support, placing each board’s logic in its own dedicated source file.
It improves maintainability, readability, and simplifies future
development for new platforms without cluttering aspeed.c
Key updates include:
- Removed QUANTA_Q71L_BMC_HW_STRAP1 macro definition from aspeed.c.
- Moved quanta_q71l_bmc_i2c_init() I²C initialization logic into the new file.
- Moved aspeed_machine_quanta_q71l_class_init() and type registration.
- Added aspeed_ast2400_quanta-q71l.c to the build system (meson.build).
- Removed all Quanta-Q71L–specific code and macros from aspeed.c.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 66 ----------------------
hw/arm/aspeed_ast2400_quanta-q71l.c | 85 +++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 86 insertions(+), 66 deletions(-)
create mode 100644 hw/arm/aspeed_ast2400_quanta-q71l.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 11c74c3e1b..3eb1d19373 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -70,19 +70,6 @@ static struct arm_boot_info aspeed_board_binfo = {
SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
-/* Quanta-Q71l hardware value */
-#define QUANTA_Q71L_BMC_HW_STRAP1 ( \
- SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
- SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
- SCU_AST2400_HW_STRAP_ACPI_DIS | \
- SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
- SCU_HW_STRAP_VGA_CLASS_CODE | \
- SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
- SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
- SCU_HW_STRAP_SPI_WIDTH | \
- SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
- SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
-
/* AST2600 evb hardware value */
#define AST2600_EVB_HW_STRAP1 0x000000C0
#define AST2600_EVB_HW_STRAP2 0x00000003
@@ -362,38 +349,6 @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
}
-static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
-
- /*
- * The quanta-q71l platform expects tmp75s which are compatible with
- * tmp105s.
- */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
-
- /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
- /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
- /* TODO: Add Memory Riser i2c mux and eeproms. */
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
-
- /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
-
- /* i2c-7 */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
- /* - i2c@0: pmbus@59 */
- /* - i2c@1: pmbus@58 */
- /* - i2c@2: pmbus@58 */
- /* - i2c@3: pmbus@59 */
-
- /* TODO: i2c-7: Add PDB FRU eeprom@52 */
- /* TODO: i2c-8: Add BMC FRU eeprom@50 */
-}
-
static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = bmc->soc;
@@ -1117,23 +1072,6 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc,
aspeed_machine_class_init_cpus_defaults(mc);
};
-static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
- amc->soc_name = "ast2400-a1";
- amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
- amc->fmc_model = "n25q256a";
- amc->spi_model = "mx25l25635e";
- amc->num_cs = 1;
- amc->i2c_init = quanta_q71l_bmc_i2c_init;
- mc->default_ram_size = 128 * MiB;
- aspeed_machine_class_init_cpus_defaults(mc);
-}
-
static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
const void *data)
{
@@ -1517,10 +1455,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_qcom_firework_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_quanta_q71l_class_init,
}, {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2400_quanta-q71l.c b/hw/arm/aspeed_ast2400_quanta-q71l.c
new file mode 100644
index 0000000000..cda0406ace
--- /dev/null
+++ b/hw/arm/aspeed_ast2400_quanta-q71l.c
@@ -0,0 +1,85 @@
+/*
+ * Quanta Q71l
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+
+/* Quanta-Q71l hardware value */
+#define QUANTA_Q71L_BMC_HW_STRAP1 ( \
+ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
+ SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \
+ SCU_AST2400_HW_STRAP_ACPI_DIS | \
+ SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \
+ SCU_HW_STRAP_VGA_CLASS_CODE | \
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \
+ SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
+ SCU_HW_STRAP_SPI_WIDTH | \
+ SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \
+ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
+
+static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+
+ /*
+ * The quanta-q71l platform expects tmp75s which are compatible with
+ * tmp105s.
+ */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f);
+
+ /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */
+ /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */
+ /* TODO: Add Memory Riser i2c mux and eeproms. */
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9546", 0x74);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "pca9548", 0x77);
+
+ /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */
+
+ /* i2c-7 */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9546", 0x70);
+ /* - i2c@0: pmbus@59 */
+ /* - i2c@1: pmbus@58 */
+ /* - i2c@2: pmbus@58 */
+ /* - i2c@3: pmbus@59 */
+
+ /* TODO: i2c-7: Add PDB FRU eeprom@52 */
+ /* TODO: i2c-8: Add BMC FRU eeprom@50 */
+}
+
+static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)";
+ amc->soc_name = "ast2400-a1";
+ amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1;
+ amc->fmc_model = "n25q256a";
+ amc->spi_model = "mx25l25635e";
+ amc->num_cs = 1;
+ amc->i2c_init = quanta_q71l_bmc_i2c_init;
+ mc->default_ram_size = 128 * MiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast2400_quanta_q71l_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_quanta_q71l_class_init,
+ }
+};
+
+DEFINE_TYPES(aspeed_ast2400_quanta_q71l_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index cbee7ebf60..4475807e11 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -44,6 +44,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed.c',
'aspeed_soc_common.c',
'aspeed_ast2400.c',
+ 'aspeed_ast2400_quanta-q71l.c',
'aspeed_ast2500_evb.c',
'aspeed_ast2500_fp5280g2.c',
'aspeed_ast2500_g220a.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 02/17] hw/arm/aspeed: Split Supermicro X11 machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 01/17] hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file " Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 03/17] hw/arm/aspeed: Split Palmetto " Jamin Lin via
` (14 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Supermicro X11 BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2400_supermicrox11.c and
removes its dependency on the Palmetto platform’s I²C initialization.
This refactor continues the modularization effort for Aspeed platform support,
ensuring that each board’s configuration resides in its own dedicated source file.
By duplicating and renaming the palmetto_bmc_i2c_init() logic into
supermicrox11_bmc_i2c_init(), this change removes unwanted coupling between
the two board definitions.
Key updates include:
- Removed SUPERMICROX11_BMC_HW_STRAP1 macro definition from aspeed.c.
- Moved aspeed_machine_supermicrox11_bmc_class_init() and type registration into a new file.
- Added a dedicated supermicrox11_bmc_i2c_init() function (copied and renamed from Palmetto’s version).
- Added the new file aspeed_ast2400_supermicrox11.c to the build system (meson.build).
- Removed all Supermicro X11–specific code and macros from aspeed.c.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 36 ------------
hw/arm/aspeed_ast2400_supermicrox11.c | 80 +++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 81 insertions(+), 36 deletions(-)
create mode 100644 hw/arm/aspeed_ast2400_supermicrox11.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 3eb1d19373..f6e9d5cda1 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -56,20 +56,6 @@ static struct arm_boot_info aspeed_board_binfo = {
SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
-/* TODO: Find the actual hardware value */
-#define SUPERMICROX11_BMC_HW_STRAP1 ( \
- SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
- SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
- SCU_AST2400_HW_STRAP_ACPI_DIS | \
- SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
- SCU_HW_STRAP_VGA_CLASS_CODE | \
- SCU_HW_STRAP_LPC_RESET_PIN | \
- SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
- SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
- SCU_HW_STRAP_SPI_WIDTH | \
- SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
- SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
-
/* AST2600 evb hardware value */
#define AST2600_EVB_HW_STRAP1 0x000000C0
#define AST2600_EVB_HW_STRAP2 0x00000003
@@ -1072,24 +1058,6 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc,
aspeed_machine_class_init_cpus_defaults(mc);
};
-static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
- amc->soc_name = "ast2400-a1";
- amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
- amc->fmc_model = "mx25l25635e";
- amc->spi_model = "mx25l25635e";
- amc->num_cs = 1;
- amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
- amc->i2c_init = palmetto_bmc_i2c_init;
- mc->default_ram_size = 256 * MiB;
- aspeed_machine_class_init_cpus_defaults(mc);
-}
-
static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
const void *data)
{
@@ -1439,10 +1407,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("palmetto-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_palmetto_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_supermicrox11_bmc_class_init,
}, {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2400_supermicrox11.c b/hw/arm/aspeed_ast2400_supermicrox11.c
new file mode 100644
index 0000000000..168a3251f0
--- /dev/null
+++ b/hw/arm/aspeed_ast2400_supermicrox11.c
@@ -0,0 +1,80 @@
+/*
+ * Supermicro X11
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/i2c/smbus_eeprom.h"
+
+/* TODO: Find the actual hardware value */
+#define SUPERMICROX11_BMC_HW_STRAP1 ( \
+ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
+ SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
+ SCU_AST2400_HW_STRAP_ACPI_DIS | \
+ SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
+ SCU_HW_STRAP_VGA_CLASS_CODE | \
+ SCU_HW_STRAP_LPC_RESET_PIN | \
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
+ SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
+ SCU_HW_STRAP_SPI_WIDTH | \
+ SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
+ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
+
+static void supermicrox11_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ DeviceState *dev;
+ uint8_t *eeprom_buf = g_malloc0(32 * 1024);
+
+ /*
+ * The palmetto platform expects a ds3231 RTC but a ds1338 is
+ * enough to provide basic RTC features. Alarms will be missing
+ */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
+
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
+ eeprom_buf);
+
+ /* add a TMP423 temperature sensor */
+ dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
+ "tmp423", 0x4c));
+ object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
+ object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
+ object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
+ object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
+}
+
+static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
+ amc->soc_name = "ast2400-a1";
+ amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
+ amc->fmc_model = "mx25l25635e";
+ amc->spi_model = "mx25l25635e";
+ amc->num_cs = 1;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
+ amc->i2c_init = supermicrox11_bmc_i2c_init;
+ mc->default_ram_size = 256 * MiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast2400_supermicrox11_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_supermicrox11_bmc_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2400_supermicrox11_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 4475807e11..9411e27d78 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -45,6 +45,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_soc_common.c',
'aspeed_ast2400.c',
'aspeed_ast2400_quanta-q71l.c',
+ 'aspeed_ast2400_supermicrox11.c',
'aspeed_ast2500_evb.c',
'aspeed_ast2500_fp5280g2.c',
'aspeed_ast2500_g220a.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 03/17] hw/arm/aspeed: Split Palmetto machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 01/17] hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 02/17] hw/arm/aspeed: Split Supermicro X11 " Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 04/17] hw/arm/aspeed: Move ASPEED_RAM_SIZE() macro to common header for reuse Jamin Lin via
` (13 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the OpenPOWER Palmetto BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2400_palmetto.c.
This refactor continues the modularization effort for Aspeed platform support,
placing each board’s logic in its own dedicated source file.
It improves maintainability, readability, and simplifies future development for
new platforms without cluttering aspeed.c.
Key updates include:
- Removed PALMETTO_BMC_HW_STRAP1 macro definition from aspeed.c.
- Moved palmetto_bmc_i2c_init() I²C initialization logic into the new file.
- Moved aspeed_machine_palmetto_class_init() and type registration.
- Added aspeed_ast2400_palmetto.c to the build system (meson.build).
- Removed all Palmetto-specific code and macros from aspeed.c.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 59 ------------------------
hw/arm/aspeed_ast2400_palmetto.c | 79 ++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 80 insertions(+), 59 deletions(-)
create mode 100644 hw/arm/aspeed_ast2400_palmetto.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index f6e9d5cda1..f58245456a 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -42,20 +42,6 @@ static struct arm_boot_info aspeed_board_binfo = {
#define ASPEED_RAM_SIZE(sz) (sz)
#endif
-/* Palmetto hardware value: 0x120CE416 */
-#define PALMETTO_BMC_HW_STRAP1 ( \
- SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
- SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
- SCU_AST2400_HW_STRAP_ACPI_DIS | \
- SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
- SCU_HW_STRAP_VGA_CLASS_CODE | \
- SCU_HW_STRAP_LPC_RESET_PIN | \
- SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
- SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
- SCU_HW_STRAP_SPI_WIDTH | \
- SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
- SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
-
/* AST2600 evb hardware value */
#define AST2600_EVB_HW_STRAP1 0x000000C0
#define AST2600_EVB_HW_STRAP2 0x00000003
@@ -311,30 +297,6 @@ static void aspeed_machine_init(MachineState *machine)
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
}
-static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
- DeviceState *dev;
- uint8_t *eeprom_buf = g_malloc0(32 * 1024);
-
- /*
- * The palmetto platform expects a ds3231 RTC but a ds1338 is
- * enough to provide basic RTC features. Alarms will be missing
- */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
-
- smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
- eeprom_buf);
-
- /* add a TMP423 temperature sensor */
- dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
- "tmp423", 0x4c));
- object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
- object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
- object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
- object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
-}
-
static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = bmc->soc;
@@ -1041,23 +1003,6 @@ static void aspeed_machine_class_init(ObjectClass *oc, const void *data)
aspeed_machine_class_props_init(oc);
}
-static void aspeed_machine_palmetto_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
- amc->soc_name = "ast2400-a1";
- amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
- amc->fmc_model = "n25q256a";
- amc->spi_model = "mx25l25635f";
- amc->num_cs = 1;
- amc->i2c_init = palmetto_bmc_i2c_init;
- mc->default_ram_size = 256 * MiB;
- aspeed_machine_class_init_cpus_defaults(mc);
-};
-
static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
const void *data)
{
@@ -1404,10 +1349,6 @@ static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
static const TypeInfo aspeed_machine_types[] = {
{
- .name = MACHINE_TYPE_NAME("palmetto-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_palmetto_class_init,
- }, {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
diff --git a/hw/arm/aspeed_ast2400_palmetto.c b/hw/arm/aspeed_ast2400_palmetto.c
new file mode 100644
index 0000000000..1c17de2088
--- /dev/null
+++ b/hw/arm/aspeed_ast2400_palmetto.c
@@ -0,0 +1,79 @@
+/*
+ * OpenPOWER Palmetto
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/i2c/smbus_eeprom.h"
+
+/* Palmetto hardware value: 0x120CE416 */
+#define PALMETTO_BMC_HW_STRAP1 ( \
+ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
+ SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
+ SCU_AST2400_HW_STRAP_ACPI_DIS | \
+ SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
+ SCU_HW_STRAP_VGA_CLASS_CODE | \
+ SCU_HW_STRAP_LPC_RESET_PIN | \
+ SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
+ SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
+ SCU_HW_STRAP_SPI_WIDTH | \
+ SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
+ SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
+
+static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ DeviceState *dev;
+ uint8_t *eeprom_buf = g_malloc0(32 * 1024);
+
+ /*
+ * The palmetto platform expects a ds3231 RTC but a ds1338 is
+ * enough to provide basic RTC features. Alarms will be missing
+ */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
+
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
+ eeprom_buf);
+
+ /* add a TMP423 temperature sensor */
+ dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
+ "tmp423", 0x4c));
+ object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
+ object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
+ object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
+ object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
+}
+
+static void aspeed_machine_palmetto_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
+ amc->soc_name = "ast2400-a1";
+ amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
+ amc->fmc_model = "n25q256a";
+ amc->spi_model = "mx25l25635f";
+ amc->num_cs = 1;
+ amc->i2c_init = palmetto_bmc_i2c_init;
+ mc->default_ram_size = 256 * MiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+};
+
+static const TypeInfo aspeed_ast2400_palmetto_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("palmetto-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_palmetto_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2400_palmetto_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 9411e27d78..293dbbb53b 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -44,6 +44,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed.c',
'aspeed_soc_common.c',
'aspeed_ast2400.c',
+ 'aspeed_ast2400_palmetto.c',
'aspeed_ast2400_quanta-q71l.c',
'aspeed_ast2400_supermicrox11.c',
'aspeed_ast2500_evb.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 04/17] hw/arm/aspeed: Move ASPEED_RAM_SIZE() macro to common header for reuse
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (2 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 03/17] hw/arm/aspeed: Split Palmetto " Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 05/17] hw/arm/aspeed: Split Bletchley machine into a separate source file for maintainability Jamin Lin via
` (12 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
Moving it into aspeed.h allows all Aspeed machine source files
(AST2400, AST2500, AST2600, AST2700, etc.) to reuse the same macro
definition for consistent behavior and maintainability.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed.h | 7 +++++++
hw/arm/aspeed.c | 7 -------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index fbe684d505..414c181c3a 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -25,6 +25,13 @@ DECLARE_OBJ_CHECKERS(AspeedMachineState, AspeedMachineClass,
#define ASPEED_MAC2_ON (1 << 2)
#define ASPEED_MAC3_ON (1 << 3)
+/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
+#if HOST_LONG_BITS == 32
+#define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
+#else
+#define ASPEED_RAM_SIZE(sz) (sz)
+#endif
+
struct AspeedMachineState {
/* Private */
MachineState parent_obj;
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index f58245456a..690ad0be87 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -35,13 +35,6 @@ static struct arm_boot_info aspeed_board_binfo = {
.board_id = -1, /* device-tree-only board */
};
-/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */
-#if HOST_LONG_BITS == 32
-#define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB)
-#else
-#define ASPEED_RAM_SIZE(sz) (sz)
-#endif
-
/* AST2600 evb hardware value */
#define AST2600_EVB_HW_STRAP1 0x000000C0
#define AST2600_EVB_HW_STRAP2 0x00000003
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 05/17] hw/arm/aspeed: Split Bletchley machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (3 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 04/17] hw/arm/aspeed: Move ASPEED_RAM_SIZE() macro to common header for reuse Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 06/17] hw/arm/aspeed: Split FBY35 BMC " Jamin Lin via
` (11 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Facebook Bletchley BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_bletchley.c.
This refactor continues the modularization effort for Aspeed platform support,
placing each board’s logic in its own dedicated source file.
It improves maintainability, readability, and simplifies future development for
new platforms without cluttering aspeed.c.
Key updates include:
- Moved BLETCHLEY_BMC_HW_STRAP1 and BLETCHLEY_BMC_HW_STRAP2 macro definitions into the new file.
- Moved bletchley_bmc_i2c_init() I²C initialization logic into the new file.
- Moved aspeed_machine_bletchley_class_init() and type registration.
- Added aspeed_ast2600_bletchley.c to the build system (meson.build).
- Removed all Bletchley-specific code and macros from aspeed.c.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 76 ------------------------
hw/arm/aspeed_ast2600_bletchley.c | 96 +++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 97 insertions(+), 76 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_bletchley.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 690ad0be87..6458798c2c 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -55,10 +55,6 @@ static struct arm_boot_info aspeed_board_binfo = {
#define FUJI_BMC_HW_STRAP1 0x00000000
#define FUJI_BMC_HW_STRAP2 0x00000000
-/* Bletchley hardware value */
-#define BLETCHLEY_BMC_HW_STRAP1 0x00002000
-#define BLETCHLEY_BMC_HW_STRAP2 0x00000801
-
/* GB200NVL hardware value */
#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
@@ -684,53 +680,6 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
at24c_eeprom_init(i2c[15], 0x52, 8 * KiB);
}
-static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
- I2CBus *i2c[13] = {};
- for (int i = 0; i < 13; i++) {
- if ((i == 8) || (i == 11)) {
- continue;
- }
- i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
- }
-
- /* Bus 0 - 5 all have the same config. */
- for (int i = 0; i < 6; i++) {
- /* Missing model: ti,ina230 @ 0x45 */
- /* Missing model: mps,mp5023 @ 0x40 */
- i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
- /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
- i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
- i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
- /* Missing model: fsc,fusb302 @ 0x22 */
- }
-
- /* Bus 6 */
- at24c_eeprom_init(i2c[6], 0x56, 65536);
- /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
- i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
-
-
- /* Bus 7 */
- at24c_eeprom_init(i2c[7], 0x54, 65536);
-
- /* Bus 9 */
- i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
-
- /* Bus 10 */
- i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
- /* Missing model: ti,hdc1080 @ 0x40 */
- i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
-
- /* Bus 12 */
- /* Missing model: adi,adm1278 @ 0x11 */
- i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
- i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
- i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
-}
-
-
static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = bmc->soc;
@@ -1058,27 +1007,6 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data)
aspeed_machine_class_init_cpus_defaults(mc);
};
-#define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
-
-static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
- amc->soc_name = "ast2600-a3";
- amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
- amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
- amc->fmc_model = "w25q01jvq";
- amc->spi_model = NULL;
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC2_ON;
- amc->i2c_init = bletchley_bmc_i2c_init;
- mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
- aspeed_machine_class_init_cpus_defaults(mc);
-}
-
static void aspeed_machine_catalina_class_init(ObjectClass *oc,
const void *data)
{
@@ -1361,10 +1289,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("fuji-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_fuji_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("bletchley-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_bletchley_class_init,
}, {
.name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2600_bletchley.c b/hw/arm/aspeed_ast2600_bletchley.c
new file mode 100644
index 0000000000..bb13970894
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_bletchley.c
@@ -0,0 +1,96 @@
+/*
+ * Facebook Bletchley
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/gpio/pca9552.h"
+#include "hw/nvram/eeprom_at24c.h"
+
+#define TYPE_TMP421 "tmp421"
+/* Bletchley hardware value */
+#define BLETCHLEY_BMC_HW_STRAP1 0x00002000
+#define BLETCHLEY_BMC_HW_STRAP2 0x00000801
+#define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
+
+static void bletchley_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ I2CBus *i2c[13] = {};
+ for (int i = 0; i < 13; i++) {
+ if ((i == 8) || (i == 11)) {
+ continue;
+ }
+ i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
+ }
+
+ /* Bus 0 - 5 all have the same config. */
+ for (int i = 0; i < 6; i++) {
+ /* Missing model: ti,ina230 @ 0x45 */
+ /* Missing model: mps,mp5023 @ 0x40 */
+ i2c_slave_create_simple(i2c[i], TYPE_TMP421, 0x4f);
+ /* Missing model: nxp,pca9539 @ 0x76, but PCA9552 works enough */
+ i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x76);
+ i2c_slave_create_simple(i2c[i], TYPE_PCA9552, 0x67);
+ /* Missing model: fsc,fusb302 @ 0x22 */
+ }
+
+ /* Bus 6 */
+ at24c_eeprom_init(i2c[6], 0x56, 65536);
+ /* Missing model: nxp,pcf85263 @ 0x51 , but ds1338 works enough */
+ i2c_slave_create_simple(i2c[6], "ds1338", 0x51);
+
+
+ /* Bus 7 */
+ at24c_eeprom_init(i2c[7], 0x54, 65536);
+
+ /* Bus 9 */
+ i2c_slave_create_simple(i2c[9], TYPE_TMP421, 0x4f);
+
+ /* Bus 10 */
+ i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x4f);
+ /* Missing model: ti,hdc1080 @ 0x40 */
+ i2c_slave_create_simple(i2c[10], TYPE_PCA9552, 0x67);
+
+ /* Bus 12 */
+ /* Missing model: adi,adm1278 @ 0x11 */
+ i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4c);
+ i2c_slave_create_simple(i2c[12], TYPE_TMP421, 0x4d);
+ i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67);
+}
+
+static void aspeed_machine_bletchley_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Facebook Bletchley BMC (Cortex-A7)";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = BLETCHLEY_BMC_HW_STRAP1;
+ amc->hw_strap2 = BLETCHLEY_BMC_HW_STRAP2;
+ amc->fmc_model = "w25q01jvq";
+ amc->spi_model = NULL;
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC2_ON;
+ amc->i2c_init = bletchley_bmc_i2c_init;
+ mc->default_ram_size = BLETCHLEY_BMC_RAM_SIZE;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast2600_bletchley_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("bletchley-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_bletchley_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_bletchley_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 293dbbb53b..06e27d94b9 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -57,6 +57,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2500_witherspoon.c',
'aspeed_ast2500_yosemitev2.c',
'aspeed_ast2600.c',
+ 'aspeed_ast2600_bletchley.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
'fby35.c'))
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 06/17] hw/arm/aspeed: Split FBY35 BMC machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (4 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 05/17] hw/arm/aspeed: Split Bletchley machine into a separate source file for maintainability Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 07/17] hw/arm/aspeed: Split Fuji " Jamin Lin via
` (10 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Facebook fby35 BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_fby35.c.
This refactor continues the modularization effort for Aspeed platform support,
placing each board’s logic in its own dedicated source file.
It improves maintainability, readability, and simplifies future development for
new platforms without cluttering aspeed.c.
Key updates include:
- Moved fby35_i2c_init() and fby35_reset() to the new file.
- Moved aspeed_machine_fby35_class_init() and machine registration to the new file.
- Removed fby35 FRU data (fby35_nic_fruid, fby35_bb_fruid, fby35_bmc_fruid) and their size definitions from aspeed_eeprom.[ch].
- Added aspeed_ast2600_fby35.c to the build system (meson.build).
- Cleaned up all fby35-specific code and declarations from aspeed.c and aspeed_eeprom.*.
- Introduced FBY35_BMC_RAM_SIZE macro based on FUJI_BMC_RAM_SIZE to remove
inter-file dependency.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_eeprom.h | 7 --
hw/arm/aspeed.c | 78 ---------------
hw/arm/aspeed_ast2600_fby35.c | 177 ++++++++++++++++++++++++++++++++++
hw/arm/aspeed_eeprom.c | 74 --------------
hw/arm/meson.build | 1 +
5 files changed, 178 insertions(+), 159 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_fby35.c
diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
index 5448eeeab7..7207bb2cbd 100644
--- a/hw/arm/aspeed_eeprom.h
+++ b/hw/arm/aspeed_eeprom.h
@@ -7,13 +7,6 @@
#ifndef ASPEED_EEPROM_H
#define ASPEED_EEPROM_H
-extern const uint8_t fby35_nic_fruid[];
-extern const uint8_t fby35_bb_fruid[];
-extern const uint8_t fby35_bmc_fruid[];
-extern const size_t fby35_nic_fruid_len;
-extern const size_t fby35_bb_fruid_len;
-extern const size_t fby35_bmc_fruid_len;
-
extern const uint8_t rainier_bb_fruid[];
extern const size_t rainier_bb_fruid_len;
extern const uint8_t rainier_bmc_fruid[];
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 6458798c2c..d9b38fcc36 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -718,38 +718,6 @@ static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
gb200nvl_bmc_fruid_len);
}
-static void fby35_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
- I2CBus *i2c[16];
-
- for (int i = 0; i < 16; i++) {
- i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
- }
-
- i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
- i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
- /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
- i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
- i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
- i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
-
- at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
- at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
- at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
- fby35_nic_fruid_len);
- at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
- fby35_bb_fruid_len);
- at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
- fby35_bmc_fruid_len);
-
- /*
- * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
- * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
- * each.
- */
-}
-
static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
{
AspeedSoCState *soc = bmc->soc;
@@ -1052,48 +1020,6 @@ static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
aspeed_machine_ast2600_class_emmc_init(oc);
}
-static void fby35_reset(MachineState *state, ResetType type)
-{
- AspeedMachineState *bmc = ASPEED_MACHINE(state);
- AspeedGPIOState *gpio = &bmc->soc->gpio;
-
- qemu_devices_reset(type);
-
- /* Board ID: 7 (Class-1, 4 slots) */
- object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
-
- /* Slot presence pins, inverse polarity. (False means present) */
- object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
-
- /* Slot 12v power pins, normal polarity. (True means powered-on) */
- object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
- object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
-}
-
-static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Facebook fby35 BMC (Cortex-A7)";
- mc->reset = fby35_reset;
- amc->fmc_model = "mx66l1g45g";
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC3_ON;
- amc->i2c_init = fby35_i2c_init;
- /* FIXME: Replace this macro with something more general */
- mc->default_ram_size = FUJI_BMC_RAM_SIZE;
- aspeed_machine_class_init_cpus_defaults(mc);
-}
-
#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
/* Main SYSCLK frequency in Hz (200MHz) */
#define SYSCLK_FRQ 200000000ULL
@@ -1297,10 +1223,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("catalina-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_catalina_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("fby35-bmc"),
- .parent = MACHINE_TYPE_NAME("ast2600-evb"),
- .class_init = aspeed_machine_fby35_class_init,
}, {
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2600_fby35.c b/hw/arm/aspeed_ast2600_fby35.c
new file mode 100644
index 0000000000..f836be4d6d
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_fby35.c
@@ -0,0 +1,177 @@
+/*
+ * Facebook fby35
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/nvram/eeprom_at24c.h"
+#include "hw/sensor/tmp105.h"
+#include "system/reset.h"
+
+#define TYPE_LM75 TYPE_TMP105
+#define TYPE_TMP421 "tmp421"
+#define FBY35_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
+
+static const uint8_t fby35_nic_fruid[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7,
+ 0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd,
+ 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f, 0x6e,
+ 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20, 0x4f,
+ 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72,
+ 0x20, 0x30, 0x2e, 0x30, 0x32, 0xc0, 0xc0, 0xc0, 0xc1, 0x00, 0x00, 0x2f,
+ 0x01, 0x11, 0x19, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0xdd, 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f,
+ 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20,
+ 0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xd3, 0x41, 0x39, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
+ 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63,
+ 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xdb, 0xc0, 0x82, 0x30, 0x15, 0x79, 0x7f, 0xa6, 0x00,
+ 0x01, 0x18, 0x0b, 0xff, 0x08, 0x00, 0xff, 0xff, 0x64, 0x00, 0x00, 0x00,
+ 0x00, 0x03, 0x20, 0x01, 0xff, 0xff, 0x04, 0x46, 0x00, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0x01, 0x81, 0x09, 0x15, 0xb3, 0x10, 0x1d, 0x00,
+ 0x24, 0x15, 0xb3, 0x00, 0x02, 0xeb, 0x8a, 0x95, 0x5c,
+};
+static const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
+
+static const uint8_t fby35_bb_fruid[] = {
+ 0x01, 0x00, 0x01, 0x03, 0x10, 0x00, 0x00, 0xeb, 0x01, 0x02, 0x17, 0xc3,
+ 0x4e, 0x2f, 0x41, 0xc3, 0x4e, 0x2f, 0x41, 0xc1, 0x00, 0x00, 0x00, 0x23,
+ 0x01, 0x0d, 0x00, 0xb6, 0xd2, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0xd5, 0x4d, 0x61, 0x6e, 0x61, 0x67, 0x65, 0x6d, 0x65, 0x6e, 0x74,
+ 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x77, 0x42, 0x4d, 0x43, 0xcd,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x01, 0x0c, 0x00, 0xc6,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
+ 0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
+ 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x4e, 0x2f,
+ 0x41, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43,
+};
+static const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
+
+static const uint8_t fby35_bmc_fruid[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
+ 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
+ 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
+ 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
+ 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
+ 0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
+ 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
+ 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
+ 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
+};
+static const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
+
+static void fby35_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ I2CBus *i2c[16];
+
+ for (int i = 0; i < 16; i++) {
+ i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
+ }
+
+ i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f);
+ i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f);
+ /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */
+ i2c_slave_create_simple(i2c[11], "adm1272", 0x44);
+ i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e);
+ i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f);
+
+ at24c_eeprom_init(i2c[4], 0x51, 128 * KiB);
+ at24c_eeprom_init(i2c[6], 0x51, 128 * KiB);
+ at24c_eeprom_init_rom(i2c[8], 0x50, 32 * KiB, fby35_nic_fruid,
+ fby35_nic_fruid_len);
+ at24c_eeprom_init_rom(i2c[11], 0x51, 128 * KiB, fby35_bb_fruid,
+ fby35_bb_fruid_len);
+ at24c_eeprom_init_rom(i2c[11], 0x54, 128 * KiB, fby35_bmc_fruid,
+ fby35_bmc_fruid_len);
+
+ /*
+ * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC on
+ * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on
+ * each.
+ */
+}
+
+static void fby35_reset(MachineState *state, ResetType type)
+{
+ AspeedMachineState *bmc = ASPEED_MACHINE(state);
+ AspeedGPIOState *gpio = &bmc->soc->gpio;
+
+ qemu_devices_reset(type);
+
+ /* Board ID: 7 (Class-1, 4 slots) */
+ object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal);
+
+ /* Slot presence pins, inverse polarity. (False means present) */
+ object_property_set_bool(OBJECT(gpio), "gpioH4", false, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioH5", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioH6", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioH7", true, &error_fatal);
+
+ /* Slot 12v power pins, normal polarity. (True means powered-on) */
+ object_property_set_bool(OBJECT(gpio), "gpioB2", true, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioB3", false, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioB4", false, &error_fatal);
+ object_property_set_bool(OBJECT(gpio), "gpioB5", false, &error_fatal);
+}
+
+static void aspeed_machine_fby35_class_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Facebook fby35 BMC (Cortex-A7)";
+ mc->reset = fby35_reset;
+ amc->fmc_model = "mx66l1g45g";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC3_ON;
+ amc->i2c_init = fby35_i2c_init;
+ mc->default_ram_size = FBY35_BMC_RAM_SIZE;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast2600_fby35_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("fby35-bmc"),
+ .parent = MACHINE_TYPE_NAME("ast2600-evb"),
+ .class_init = aspeed_machine_fby35_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_fby35_types)
+
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
index 124277eaca..53c9b0d56f 100644
--- a/hw/arm/aspeed_eeprom.c
+++ b/hw/arm/aspeed_eeprom.c
@@ -7,77 +7,6 @@
#include "qemu/osdep.h"
#include "aspeed_eeprom.h"
-const uint8_t fby35_nic_fruid[] = {
- 0x01, 0x00, 0x00, 0x01, 0x0f, 0x20, 0x00, 0xcf, 0x01, 0x0e, 0x19, 0xd7,
- 0x5e, 0xcf, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xdd,
- 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f, 0x6e,
- 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20, 0x4f,
- 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0xcc, 0x46, 0x52, 0x55, 0x20, 0x56, 0x65, 0x72,
- 0x20, 0x30, 0x2e, 0x30, 0x32, 0xc0, 0xc0, 0xc0, 0xc1, 0x00, 0x00, 0x2f,
- 0x01, 0x11, 0x19, 0xc8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0xdd, 0x4d, 0x65, 0x6c, 0x6c, 0x61, 0x6e, 0x6f, 0x78, 0x20, 0x43, 0x6f,
- 0x6e, 0x6e, 0x65, 0x63, 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0x20,
- 0x4f, 0x43, 0x50, 0x33, 0x2e, 0x30, 0xd5, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0xd3, 0x41, 0x39, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
- 0xd8, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0xc0, 0xc0, 0xc0, 0xc0, 0xcd, 0x43, 0x6f, 0x6e, 0x6e, 0x65, 0x63,
- 0x74, 0x58, 0x2d, 0x36, 0x20, 0x44, 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0xdb, 0xc0, 0x82, 0x30, 0x15, 0x79, 0x7f, 0xa6, 0x00,
- 0x01, 0x18, 0x0b, 0xff, 0x08, 0x00, 0xff, 0xff, 0x64, 0x00, 0x00, 0x00,
- 0x00, 0x03, 0x20, 0x01, 0xff, 0xff, 0x04, 0x46, 0x00, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0x01, 0x81, 0x09, 0x15, 0xb3, 0x10, 0x1d, 0x00,
- 0x24, 0x15, 0xb3, 0x00, 0x02, 0xeb, 0x8a, 0x95, 0x5c,
-};
-
-const uint8_t fby35_bb_fruid[] = {
- 0x01, 0x00, 0x01, 0x03, 0x10, 0x00, 0x00, 0xeb, 0x01, 0x02, 0x17, 0xc3,
- 0x4e, 0x2f, 0x41, 0xc3, 0x4e, 0x2f, 0x41, 0xc1, 0x00, 0x00, 0x00, 0x23,
- 0x01, 0x0d, 0x00, 0xb6, 0xd2, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0xd5, 0x4d, 0x61, 0x6e, 0x61, 0x67, 0x65, 0x6d, 0x65, 0x6e, 0x74,
- 0x20, 0x42, 0x6f, 0x61, 0x72, 0x64, 0x20, 0x77, 0x42, 0x4d, 0x43, 0xcd,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0x01, 0x0c, 0x00, 0xc6,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
- 0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
- 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x4e, 0x2f,
- 0x41, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43,
-};
-
-const uint8_t fby35_bmc_fruid[] = {
- 0x01, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0xf1, 0x01, 0x0c, 0x00, 0x36,
- 0xe6, 0xd0, 0xc6, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x42, 0x4d,
- 0x43, 0x20, 0x53, 0x74, 0x6f, 0x72, 0x61, 0x67, 0x65, 0x20, 0x4d, 0x6f,
- 0x64, 0x75, 0x6c, 0x65, 0xcd, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e,
- 0x30, 0xc9, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc1, 0x39, 0x01, 0x0c, 0x00, 0xc6,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xd2, 0x59, 0x6f, 0x73, 0x65, 0x6d,
- 0x69, 0x74, 0x65, 0x20, 0x56, 0x33, 0x2e, 0x35, 0x20, 0x45, 0x56, 0x54,
- 0x32, 0xce, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0xc4, 0x45, 0x56, 0x54, 0x32, 0xcd, 0x58, 0x58,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc7,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc3, 0x31, 0x2e, 0x30, 0xc9,
- 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0x58, 0xc8, 0x43, 0x6f,
- 0x6e, 0x66, 0x69, 0x67, 0x20, 0x41, 0xc1, 0x45,
-};
-
const uint8_t rainier_bb_fruid[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84,
0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02,
@@ -139,9 +68,6 @@ const uint8_t gb200nvl_bmc_fruid[] = {
};
-const size_t fby35_nic_fruid_len = sizeof(fby35_nic_fruid);
-const size_t fby35_bb_fruid_len = sizeof(fby35_bb_fruid);
-const size_t fby35_bmc_fruid_len = sizeof(fby35_bmc_fruid);
const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 06e27d94b9..82ab04ff1c 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -58,6 +58,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2500_yosemitev2.c',
'aspeed_ast2600.c',
'aspeed_ast2600_bletchley.c',
+ 'aspeed_ast2600_fby35.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
'fby35.c'))
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 07/17] hw/arm/aspeed: Split Fuji machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (5 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 06/17] hw/arm/aspeed: Split FBY35 BMC " Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 08/17] hw/arm/aspeed: Split QCOM Firework " Jamin Lin via
` (9 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Facebook Fuji BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_fuji.c.
This refactor continues the modularization effort for Aspeed platform support,
placing each board’s logic in its own dedicated source file.
It improves maintainability, readability, and simplifies future development for
new platforms without cluttering aspeed.c.
Key updates include:
- Moved FUJI_BMC_HW_STRAP1 and FUJI_BMC_HW_STRAP2 macro definitions into the new file.
- Moved fuji_bmc_i2c_init() and its helper get_pca9548_channels() into the new file.
- Moved aspeed_machine_fuji_class_init() and type registration to aspeed_ast2600_fuji.c.
- Added aspeed_ast2600_fuji.c to the build system (meson.build).
- Cleaned up all Fuji-specific code and macros from aspeed.c.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 116 -----------------------------
hw/arm/aspeed_ast2600_fuji.c | 139 +++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 140 insertions(+), 116 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_fuji.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index d9b38fcc36..1f35706050 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -51,10 +51,6 @@ static struct arm_boot_info aspeed_board_binfo = {
#define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
#define RAINIER_BMC_HW_STRAP2 0x80000848
-/* Fuji hardware value */
-#define FUJI_BMC_HW_STRAP1 0x00000000
-#define FUJI_BMC_HW_STRAP2 0x00000000
-
/* GB200NVL hardware value */
#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
@@ -415,95 +411,8 @@ static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
create_pca9552(soc, 15, 0x60);
}
-static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
- I2CBus **channels)
-{
- I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
- for (int i = 0; i < 8; i++) {
- channels[i] = pca954x_i2c_get_bus(mux, i);
- }
-}
-
#define TYPE_LM75 TYPE_TMP105
#define TYPE_TMP75 TYPE_TMP105
-#define TYPE_TMP422 "tmp422"
-
-static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
- I2CBus *i2c[144] = {};
-
- for (int i = 0; i < 16; i++) {
- i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
- }
- I2CBus *i2c180 = i2c[2];
- I2CBus *i2c480 = i2c[8];
- I2CBus *i2c600 = i2c[11];
-
- get_pca9548_channels(i2c180, 0x70, &i2c[16]);
- get_pca9548_channels(i2c480, 0x70, &i2c[24]);
- /* NOTE: The device tree skips [32, 40) in the alias numbering */
- get_pca9548_channels(i2c600, 0x77, &i2c[40]);
- get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
- get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
- get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
- get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
- for (int i = 0; i < 8; i++) {
- get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
- }
-
- i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
- i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
-
- /*
- * EEPROM 24c64 size is 64Kbits or 8 Kbytes
- * 24c02 size is 2Kbits or 256 bytes
- */
- at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[20], 0x50, 256);
- at24c_eeprom_init(i2c[22], 0x52, 256);
-
- i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
- i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
- i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
- i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
-
- at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
- i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
-
- i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
- at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
- i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
- i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
-
- i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
- i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
-
- at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
- i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
- i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
- at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
-
- at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
- i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
- i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
- at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
- at24c_eeprom_init(i2c[28], 0x50, 256);
-
- for (int i = 0; i < 8; i++) {
- at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
- i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
- i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
- i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
- }
-}
-
#define TYPE_TMP421 "tmp421"
#define TYPE_DS1338 "ds1338"
@@ -954,27 +863,6 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data)
aspeed_machine_ast2600_class_emmc_init(oc);
};
-#define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
-
-static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Facebook Fuji BMC (Cortex-A7)";
- amc->soc_name = "ast2600-a3";
- amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
- amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
- amc->fmc_model = "mx66l1g45g";
- amc->spi_model = "mx66l1g45g";
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC3_ON;
- amc->i2c_init = fuji_bmc_i2c_init;
- amc->uart_default = ASPEED_DEV_UART1;
- mc->default_ram_size = FUJI_BMC_RAM_SIZE;
- aspeed_machine_class_init_cpus_defaults(mc);
-};
-
static void aspeed_machine_catalina_class_init(ObjectClass *oc,
const void *data)
{
@@ -1211,10 +1099,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_rainier_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("fuji-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_fuji_class_init,
}, {
.name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2600_fuji.c b/hw/arm/aspeed_ast2600_fuji.c
new file mode 100644
index 0000000000..78d234ca6f
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_fuji.c
@@ -0,0 +1,139 @@
+/*
+ * Facebook Fuji
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/i2c/i2c_mux_pca954x.h"
+#include "hw/sensor/tmp105.h"
+#include "hw/nvram/eeprom_at24c.h"
+
+#define TYPE_LM75 TYPE_TMP105
+#define TYPE_TMP75 TYPE_TMP105
+#define TYPE_TMP422 "tmp422"
+
+/* Fuji hardware value */
+#define FUJI_BMC_HW_STRAP1 0x00000000
+#define FUJI_BMC_HW_STRAP2 0x00000000
+#define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
+
+static void get_pca9548_channels(I2CBus *bus, uint8_t mux_addr,
+ I2CBus **channels)
+{
+ I2CSlave *mux = i2c_slave_create_simple(bus, "pca9548", mux_addr);
+ for (int i = 0; i < 8; i++) {
+ channels[i] = pca954x_i2c_get_bus(mux, i);
+ }
+}
+
+static void fuji_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ I2CBus *i2c[144] = {};
+
+ for (int i = 0; i < 16; i++) {
+ i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
+ }
+ I2CBus *i2c180 = i2c[2];
+ I2CBus *i2c480 = i2c[8];
+ I2CBus *i2c600 = i2c[11];
+
+ get_pca9548_channels(i2c180, 0x70, &i2c[16]);
+ get_pca9548_channels(i2c480, 0x70, &i2c[24]);
+ /* NOTE: The device tree skips [32, 40) in the alias numbering */
+ get_pca9548_channels(i2c600, 0x77, &i2c[40]);
+ get_pca9548_channels(i2c[24], 0x71, &i2c[48]);
+ get_pca9548_channels(i2c[25], 0x72, &i2c[56]);
+ get_pca9548_channels(i2c[26], 0x76, &i2c[64]);
+ get_pca9548_channels(i2c[27], 0x76, &i2c[72]);
+ for (int i = 0; i < 8; i++) {
+ get_pca9548_channels(i2c[40 + i], 0x76, &i2c[80 + i * 8]);
+ }
+
+ i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4c);
+ i2c_slave_create_simple(i2c[17], TYPE_LM75, 0x4d);
+
+ /*
+ * EEPROM 24c64 size is 64Kbits or 8 Kbytes
+ * 24c02 size is 2Kbits or 256 bytes
+ */
+ at24c_eeprom_init(i2c[19], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[20], 0x50, 256);
+ at24c_eeprom_init(i2c[22], 0x52, 256);
+
+ i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x48);
+ i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x49);
+ i2c_slave_create_simple(i2c[3], TYPE_LM75, 0x4a);
+ i2c_slave_create_simple(i2c[3], TYPE_TMP422, 0x4c);
+
+ at24c_eeprom_init(i2c[8], 0x51, 8 * KiB);
+ i2c_slave_create_simple(i2c[8], TYPE_LM75, 0x4a);
+
+ i2c_slave_create_simple(i2c[50], TYPE_LM75, 0x4c);
+ at24c_eeprom_init(i2c[50], 0x52, 8 * KiB);
+ i2c_slave_create_simple(i2c[51], TYPE_TMP75, 0x48);
+ i2c_slave_create_simple(i2c[52], TYPE_TMP75, 0x49);
+
+ i2c_slave_create_simple(i2c[59], TYPE_TMP75, 0x48);
+ i2c_slave_create_simple(i2c[60], TYPE_TMP75, 0x49);
+
+ at24c_eeprom_init(i2c[65], 0x53, 8 * KiB);
+ i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x49);
+ i2c_slave_create_simple(i2c[66], TYPE_TMP75, 0x48);
+ at24c_eeprom_init(i2c[68], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[69], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[70], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[71], 0x52, 8 * KiB);
+
+ at24c_eeprom_init(i2c[73], 0x53, 8 * KiB);
+ i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x49);
+ i2c_slave_create_simple(i2c[74], TYPE_TMP75, 0x48);
+ at24c_eeprom_init(i2c[76], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[77], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[78], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[79], 0x52, 8 * KiB);
+ at24c_eeprom_init(i2c[28], 0x50, 256);
+
+ for (int i = 0; i < 8; i++) {
+ at24c_eeprom_init(i2c[81 + i * 8], 0x56, 64 * KiB);
+ i2c_slave_create_simple(i2c[82 + i * 8], TYPE_TMP75, 0x48);
+ i2c_slave_create_simple(i2c[83 + i * 8], TYPE_TMP75, 0x4b);
+ i2c_slave_create_simple(i2c[84 + i * 8], TYPE_TMP75, 0x4a);
+ }
+}
+
+static void aspeed_machine_fuji_class_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Facebook Fuji BMC (Cortex-A7)";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = FUJI_BMC_HW_STRAP1;
+ amc->hw_strap2 = FUJI_BMC_HW_STRAP2;
+ amc->fmc_model = "mx66l1g45g";
+ amc->spi_model = "mx66l1g45g";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC3_ON;
+ amc->i2c_init = fuji_bmc_i2c_init;
+ amc->uart_default = ASPEED_DEV_UART1;
+ mc->default_ram_size = FUJI_BMC_RAM_SIZE;
+ aspeed_machine_class_init_cpus_defaults(mc);
+};
+
+static const TypeInfo aspeed_ast2600_fuji_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("fuji-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_fuji_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_fuji_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 82ab04ff1c..c22b692260 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -59,6 +59,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600.c',
'aspeed_ast2600_bletchley.c',
'aspeed_ast2600_fby35.c',
+ 'aspeed_ast2600_fuji.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
'fby35.c'))
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 08/17] hw/arm/aspeed: Split QCOM Firework machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (6 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 07/17] hw/arm/aspeed: Split Fuji " Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 09/17] hw/arm/aspeed: Split QCOM DC-SCM V1 " Jamin Lin via
` (8 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the QCOM Firework BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_qcom-firework.c.
This refactor continues the modularization effort for Aspeed platform support,
placing each board’s logic in its own dedicated source file. It improves
maintainability, readability, and simplifies future development for new
platforms without cluttering aspeed.c.
Key updates include:
- Removed qcom_dc_scm_firework_i2c_init() and its Firework-specific devices
from aspeed.c.
- Removed aspeed_machine_qcom_firework_class_init() and its type registration
("qcom-firework-bmc") from aspeed_machine_types[].
- Added new source file aspeed_ast2600_qcom-firework.c containing the
Firework-specific initialization and machine class definition.
- Updated hw/arm/meson.build to include aspeed_ast2600_qcom-firework.c.
- Cleaned up all Firework-specific code from aspeed.c.
- Renamed `QCOM_DC_SCM_V1_BMC_HW_STRAP1` to
`QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP1` to avoid dependency conflicts with
other QCOM DC-SCM machines.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 56 -----------------
hw/arm/aspeed_ast2600_qcom-firework.c | 90 +++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 91 insertions(+), 56 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_qcom-firework.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 1f35706050..8d02678659 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -634,38 +634,6 @@ static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
}
-static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
- I2CSlave *therm_mux, *cpuvr_mux;
-
- /* Create the generic DC-SCM hardware */
- qcom_dc_scm_bmc_i2c_init(bmc);
-
- /* Now create the Firework specific hardware */
-
- /* I2C7 CPUVR MUX */
- cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
- "pca9546", 0x70);
- i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
- i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
- i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
- i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
-
- /* I2C8 Thermal Diodes*/
- therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
- "pca9548", 0x70);
- i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
- i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
- i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
- i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
- i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
-
- /* I2C9 Fan Controller (MAX31785) */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
-}
-
static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
{
return ASPEED_MACHINE(obj)->mmio_exec;
@@ -1062,26 +1030,6 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
aspeed_machine_class_init_cpus_defaults(mc);
};
-static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
- mc->deprecation_reason = "use 'ast2600-evb' instead";
- amc->soc_name = "ast2600-a3";
- amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
- amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
- amc->fmc_model = "n25q512a";
- amc->spi_model = "n25q512a";
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
- amc->i2c_init = qcom_dc_scm_firework_i2c_init;
- mc->default_ram_size = 1 * GiB;
- aspeed_machine_class_init_cpus_defaults(mc);
-};
-
static const TypeInfo aspeed_machine_types[] = {
{
.name = MACHINE_TYPE_NAME("ast2600-evb"),
@@ -1091,10 +1039,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_qcom_firework_class_init,
}, {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2600_qcom-firework.c b/hw/arm/aspeed_ast2600_qcom-firework.c
new file mode 100644
index 0000000000..c9cfccda1f
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_qcom-firework.c
@@ -0,0 +1,90 @@
+/*
+ * Qualcomm DC-SCM V1/Firework
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/i2c/i2c_mux_pca954x.h"
+#include "hw/sensor/tmp105.h"
+
+/* Qualcomm DC-SCM Firework hardware value */
+#define QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP1 0x00000000
+#define QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP2 0x00000041
+
+#define TYPE_LM75 TYPE_TMP105
+
+static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
+}
+
+static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ I2CSlave *therm_mux, *cpuvr_mux;
+
+ /* Create the generic DC-SCM hardware */
+ qcom_dc_scm_bmc_i2c_init(bmc);
+
+ /* Now create the Firework specific hardware */
+
+ /* I2C7 CPUVR MUX */
+ cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
+ "pca9546", 0x70);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72);
+
+ /* I2C8 Thermal Diodes*/
+ therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
+ "pca9548", 0x70);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48);
+ i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48);
+
+ /* I2C9 Fan Controller (MAX31785) */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54);
+}
+
+static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)";
+ mc->deprecation_reason = "use 'ast2600-evb' instead";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP1;
+ amc->hw_strap2 = QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP2;
+ amc->fmc_model = "n25q512a";
+ amc->spi_model = "n25q512a";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
+ amc->i2c_init = qcom_dc_scm_firework_i2c_init;
+ mc->default_ram_size = 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+};
+
+static const TypeInfo aspeed_ast2600_qcom_firework_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("qcom-firework-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_qcom_firework_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_qcom_firework_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index c22b692260..89d2f05bd2 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -60,6 +60,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_bletchley.c',
'aspeed_ast2600_fby35.c',
'aspeed_ast2600_fuji.c',
+ 'aspeed_ast2600_qcom-firework.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
'fby35.c'))
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 09/17] hw/arm/aspeed: Split QCOM DC-SCM V1 machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (7 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 08/17] hw/arm/aspeed: Split QCOM Firework " Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 10/17] hw/arm/aspeed: Make aspeed_machine_ast2600_class_emmc_init() a common API for eMMC boot setup Jamin Lin via
` (7 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the QCOM DC-SCM V1 BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_qcom-dc-scm-v1.c.
This refactor continues the modularization effort for Aspeed platform support,
placing each board’s logic in its own dedicated source file. It improves
maintainability, readability, and simplifies future development for new
platforms without cluttering aspeed.c.
Key updates include:
- Moved QCOM_DC_SCM_V1_BMC_HW_STRAP1 and QCOM_DC_SCM_V1_BMC_HW_STRAP2 macro
into the new file aspeed_ast2600_qcom-dc-scm-v1.c.
- Moved qcom_dc_scm_bmc_i2c_init() and aspeed_machine_qcom_dc_scm_v1_class_init()
into the new file aspeed_ast2600_qcom-dc-scm-v1.c.
- Moved "qcom-dc-scm-v1-bmc" machine type registration from aspeed.c to the new file.
- Updated hw/arm/meson.build to include aspeed_ast2600_qcom-dc-scm-v1.c.
- Cleaned up all QCOM DC-SCM V1-specific code from aspeed.c.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 35 -----------------
hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c | 54 ++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 55 insertions(+), 35 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 8d02678659..821a18b16c 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -55,10 +55,6 @@ static struct arm_boot_info aspeed_board_binfo = {
#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
-/* Qualcomm DC-SCM hardware value */
-#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
-#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
-
#define AST_SMP_MAILBOX_BASE 0x1e6e2180
#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
@@ -627,13 +623,6 @@ static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
gb200nvl_bmc_fruid_len);
}
-static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
-}
-
static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
{
return ASPEED_MACHINE(obj)->mmio_exec;
@@ -1010,35 +999,11 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
}
#endif
-static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
- mc->deprecation_reason = "use 'ast2600-evb' instead";
- amc->soc_name = "ast2600-a3";
- amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
- amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
- amc->fmc_model = "n25q512a";
- amc->spi_model = "n25q512a";
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
- amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
- mc->default_ram_size = 1 * GiB;
- aspeed_machine_class_init_cpus_defaults(mc);
-};
-
static const TypeInfo aspeed_machine_types[] = {
{
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
}, {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c b/hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c
new file mode 100644
index 0000000000..f022a382d4
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_qcom-dc-scm-v1.c
@@ -0,0 +1,54 @@
+/*
+ * Qualcomm DC-SCM V1
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+
+/* Qualcomm DC-SCM hardware value */
+#define QCOM_DC_SCM_V1_BMC_HW_STRAP1 0x00000000
+#define QCOM_DC_SCM_V1_BMC_HW_STRAP2 0x00000041
+
+static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d);
+}
+
+static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Qualcomm DC-SCM V1 BMC (Cortex A7)";
+ mc->deprecation_reason = "use 'ast2600-evb' instead";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1;
+ amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2;
+ amc->fmc_model = "n25q512a";
+ amc->spi_model = "n25q512a";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
+ amc->i2c_init = qcom_dc_scm_bmc_i2c_init;
+ mc->default_ram_size = 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+};
+
+static const TypeInfo aspeed_ast2600_qcom_dc_scm_v1_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_qcom_dc_scm_v1_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_qcom_dc_scm_v1_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 89d2f05bd2..2813698918 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -60,6 +60,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_bletchley.c',
'aspeed_ast2600_fby35.c',
'aspeed_ast2600_fuji.c',
+ 'aspeed_ast2600_qcom-dc-scm-v1.c',
'aspeed_ast2600_qcom-firework.c',
'aspeed_ast10x0.c',
'aspeed_eeprom.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 10/17] hw/arm/aspeed: Make aspeed_machine_ast2600_class_emmc_init() a common API for eMMC boot setup
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (8 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 09/17] hw/arm/aspeed: Split QCOM DC-SCM V1 " Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 11/17] hw/arm/aspeed: Split GB200NVL machine into a separate source file for maintainability Jamin Lin via
` (6 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit exposes the function aspeed_machine_ast2600_class_emmc_init() as
a common API so that other AST2600-based machine implementations can reuse it
to enable the "boot-emmc" property.
Previously, this function was defined as a static helper within aspeed.c,
limiting its visibility to that file. By making it global and declaring it in
aspeed.h, other machine definition files (e.g., for specific AST2600 boards)
can now easily call this API to register eMMC boot configuration support.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed.h | 1 +
hw/arm/aspeed.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index 414c181c3a..02f0ea5522 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -69,5 +69,6 @@ struct AspeedMachineClass {
void aspeed_machine_class_init_cpus_defaults(MachineClass *mc);
void create_pca9552(AspeedSoCState *soc, int bus_id, int addr);
I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr);
+void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc);
#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 821a18b16c..8a6a5b3e91 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -754,7 +754,7 @@ static void aspeed_machine_ast2600_set_boot_from_emmc(Object *obj, bool value,
}
}
-static void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc)
+void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc)
{
object_class_property_add_bool(oc, "boot-emmc",
aspeed_machine_ast2600_get_boot_from_emmc,
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 11/17] hw/arm/aspeed: Split GB200NVL machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (9 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 10/17] hw/arm/aspeed: Make aspeed_machine_ast2600_class_emmc_init() a common API for eMMC boot setup Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 12/17] hw/arm/aspeed: Split Rainier " Jamin Lin via
` (5 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Nvidia GB200NVL BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_gb200nvl.c.
This refactor continues the modularization effort for Aspeed platform support,
placing each board’s initialization logic in its own dedicated source file.
It improves code maintainability, readability, and simplifies adding new
platforms without increasing the complexity of aspeed.c.
Key updates include:
- Moved GB200NVL_BMC_HW_STRAP1 and GB200NVL_BMC_HW_STRAP2 macro definitions into the new file.
- Moved gb200nvl_bmc_i2c_init() and its related FRUID setup into the new file.
- Moved aspeed_machine_gb200nvl_class_init() and type registration logic out of aspeed.c.
- Removed gb200nvl_bmc_fruid[] and its length definition from aspeed_eeprom.c/h.
- Added aspeed_ast2600_gb200nvl.c to the Meson build system (meson.build).
- Cleaned up all GB200NVL-specific code and data from aspeed.c and aspeed_eeprom.c.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_eeprom.h | 3 -
hw/arm/aspeed.c | 71 --------------------
hw/arm/aspeed_ast2600_gb200nvl.c | 110 +++++++++++++++++++++++++++++++
hw/arm/aspeed_eeprom.c | 20 ------
hw/arm/meson.build | 1 +
5 files changed, 111 insertions(+), 94 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_gb200nvl.c
diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
index 7207bb2cbd..86b97e4c6d 100644
--- a/hw/arm/aspeed_eeprom.h
+++ b/hw/arm/aspeed_eeprom.h
@@ -12,7 +12,4 @@ extern const size_t rainier_bb_fruid_len;
extern const uint8_t rainier_bmc_fruid[];
extern const size_t rainier_bmc_fruid_len;
-extern const uint8_t gb200nvl_bmc_fruid[];
-extern const size_t gb200nvl_bmc_fruid_len;
-
#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 8a6a5b3e91..f508280050 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -51,10 +51,6 @@ static struct arm_boot_info aspeed_board_binfo = {
#define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
#define RAINIER_BMC_HW_STRAP2 0x80000848
-/* GB200NVL hardware value */
-#define GB200NVL_BMC_HW_STRAP1 AST2600_EVB_HW_STRAP1
-#define GB200NVL_BMC_HW_STRAP2 AST2600_EVB_HW_STRAP2
-
#define AST_SMP_MAILBOX_BASE 0x1e6e2180
#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
@@ -585,44 +581,6 @@ static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
at24c_eeprom_init(i2c[15], 0x52, 8 * KiB);
}
-static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
- I2CBus *i2c[15] = {};
- DeviceState *dev;
- for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
- if ((i == 11) || (i == 12) || (i == 13)) {
- continue;
- }
- i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
- }
-
- /* Bus 5 Expander */
- create_pca9554(soc, 4, 0x21);
-
- /* Mux I2c Expanders */
- i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
- i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
- i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
- i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
- i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
- i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
-
- /* Bus 10 */
- dev = DEVICE(create_pca9554(soc, 9, 0x20));
-
- /* Set FPGA_READY */
- object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
-
- create_pca9554(soc, 9, 0x21);
- at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
- at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
-
- /* Bus 11 */
- at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
- gb200nvl_bmc_fruid_len);
-}
-
static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
{
return ASPEED_MACHINE(obj)->mmio_exec;
@@ -840,31 +798,6 @@ static void aspeed_machine_catalina_class_init(ObjectClass *oc,
aspeed_machine_ast2600_class_emmc_init(oc);
}
-#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
-
-static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)";
- amc->soc_name = "ast2600-a3";
- amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
- amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
- amc->fmc_model = "mx66u51235f";
- amc->spi_model = "mx66u51235f";
- amc->num_cs = 2;
-
- amc->spi2_model = "mx66u51235f";
- amc->num_cs2 = 1;
- amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
- amc->i2c_init = gb200nvl_bmc_i2c_init;
- mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
- aspeed_machine_class_init_cpus_defaults(mc);
- aspeed_machine_ast2600_class_emmc_init(oc);
-}
-
#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
/* Main SYSCLK frequency in Hz (200MHz) */
#define SYSCLK_FRQ 200000000ULL
@@ -1008,10 +941,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_rainier_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_gb200nvl_class_init,
}, {
.name = MACHINE_TYPE_NAME("catalina-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2600_gb200nvl.c b/hw/arm/aspeed_ast2600_gb200nvl.c
new file mode 100644
index 0000000000..4ecf7e6c00
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_gb200nvl.c
@@ -0,0 +1,110 @@
+/*
+ * Nvidia GB200NVL
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/nvram/eeprom_at24c.h"
+
+/* GB200NVL hardware value */
+#define GB200NVL_BMC_HW_STRAP1 0x000000C0
+#define GB200NVL_BMC_HW_STRAP2 0x00000003
+#define GB200NVL_BMC_RAM_SIZE ASPEED_RAM_SIZE(1 * GiB)
+
+static const uint8_t gb200nvl_bmc_fruid[] = {
+ 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
+ 0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
+ 0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
+ 0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
+ 0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
+ 0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
+ 0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
+ 0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
+ 0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
+ 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
+ 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
+ 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
+ 0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+
+};
+static const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
+
+static void gb200nvl_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ I2CBus *i2c[15] = {};
+ DeviceState *dev;
+ for (int i = 0; i < sizeof(i2c) / sizeof(i2c[0]); i++) {
+ if ((i == 11) || (i == 12) || (i == 13)) {
+ continue;
+ }
+ i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
+ }
+
+ /* Bus 5 Expander */
+ create_pca9554(soc, 4, 0x21);
+
+ /* Mux I2c Expanders */
+ i2c_slave_create_simple(i2c[5], "pca9546", 0x71);
+ i2c_slave_create_simple(i2c[5], "pca9546", 0x72);
+ i2c_slave_create_simple(i2c[5], "pca9546", 0x73);
+ i2c_slave_create_simple(i2c[5], "pca9546", 0x75);
+ i2c_slave_create_simple(i2c[5], "pca9546", 0x76);
+ i2c_slave_create_simple(i2c[5], "pca9546", 0x77);
+
+ /* Bus 10 */
+ dev = DEVICE(create_pca9554(soc, 9, 0x20));
+
+ /* Set FPGA_READY */
+ object_property_set_str(OBJECT(dev), "pin1", "high", &error_fatal);
+
+ create_pca9554(soc, 9, 0x21);
+ at24c_eeprom_init(i2c[9], 0x50, 64 * KiB);
+ at24c_eeprom_init(i2c[9], 0x51, 64 * KiB);
+
+ /* Bus 11 */
+ at24c_eeprom_init_rom(i2c[10], 0x50, 256, gb200nvl_bmc_fruid,
+ gb200nvl_bmc_fruid_len);
+}
+
+static void aspeed_machine_gb200nvl_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Nvidia GB200NVL BMC (Cortex-A7)";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = GB200NVL_BMC_HW_STRAP1;
+ amc->hw_strap2 = GB200NVL_BMC_HW_STRAP2;
+ amc->fmc_model = "mx66u51235f";
+ amc->spi_model = "mx66u51235f";
+ amc->num_cs = 2;
+
+ amc->spi2_model = "mx66u51235f";
+ amc->num_cs2 = 1;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
+ amc->i2c_init = gb200nvl_bmc_i2c_init;
+ mc->default_ram_size = GB200NVL_BMC_RAM_SIZE;
+ aspeed_machine_class_init_cpus_defaults(mc);
+ aspeed_machine_ast2600_class_emmc_init(oc);
+}
+
+static const TypeInfo aspeed_ast2600_gb200nvl_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_gb200nvl_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_gb200nvl_types)
+
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
index 53c9b0d56f..85a2aa4036 100644
--- a/hw/arm/aspeed_eeprom.c
+++ b/hw/arm/aspeed_eeprom.c
@@ -49,26 +49,6 @@ const uint8_t rainier_bmc_fruid[] = {
0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
};
-const uint8_t gb200nvl_bmc_fruid[] = {
- 0x01, 0x00, 0x00, 0x01, 0x0b, 0x00, 0x00, 0xf3, 0x01, 0x0a, 0x19, 0x1f,
- 0x0f, 0xe6, 0xc6, 0x4e, 0x56, 0x49, 0x44, 0x49, 0x41, 0xc5, 0x50, 0x33,
- 0x38, 0x30, 0x39, 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38,
- 0x30, 0x30, 0x31, 0x35, 0x30, 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33,
- 0x38, 0x30, 0x39, 0x2d, 0x30, 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30,
- 0xc0, 0x01, 0x01, 0xd6, 0x4d, 0x41, 0x43, 0x3a, 0x20, 0x33, 0x43, 0x3a,
- 0x36, 0x44, 0x3a, 0x36, 0x36, 0x3a, 0x31, 0x34, 0x3a, 0x43, 0x38, 0x3a,
- 0x37, 0x41, 0xc1, 0x3b, 0x01, 0x09, 0x19, 0xc6, 0x4e, 0x56, 0x49, 0x44,
- 0x49, 0x41, 0xc9, 0x50, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x42, 0x4d, 0x43,
- 0xd2, 0x36, 0x39, 0x39, 0x2d, 0x31, 0x33, 0x38, 0x30, 0x39, 0x2d, 0x30,
- 0x34, 0x30, 0x34, 0x2d, 0x36, 0x30, 0x30, 0xc4, 0x41, 0x45, 0x2e, 0x31,
- 0xcd, 0x31, 0x35, 0x38, 0x33, 0x33, 0x32, 0x34, 0x38, 0x30, 0x30, 0x31,
- 0x35, 0x30, 0xc0, 0xc4, 0x76, 0x30, 0x2e, 0x31, 0xc1, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0xb4, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
-
-};
-
const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
-const size_t gb200nvl_bmc_fruid_len = sizeof(gb200nvl_bmc_fruid);
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 2813698918..5f6036fdb0 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -60,6 +60,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_bletchley.c',
'aspeed_ast2600_fby35.c',
'aspeed_ast2600_fuji.c',
+ 'aspeed_ast2600_gb200nvl.c',
'aspeed_ast2600_qcom-dc-scm-v1.c',
'aspeed_ast2600_qcom-firework.c',
'aspeed_ast10x0.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 12/17] hw/arm/aspeed: Split Rainier machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (10 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 11/17] hw/arm/aspeed: Split GB200NVL machine into a separate source file for maintainability Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 13/17] hw/arm/aspeed: Split Catalina " Jamin Lin via
` (4 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the IBM Rainier BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_rainier.c.
This refactor continues the modularization effort for Aspeed platform
support, placing each board’s logic and FRUID data in its own dedicated
source file. It improves maintainability, readability, and simplifies
future development for new Aspeed-based systems without cluttering
aspeed.c.
Key updates include:
- Removed RAINIER_BMC_HW_STRAP1 and RAINIER_BMC_HW_STRAP2 macro definitions.
- Moved rainier_bmc_i2c_init() and all related I2C device setup code
into the new aspeed_ast2600_rainier.c file.
- Moved aspeed_machine_rainier_class_init() and type registration logic
out of aspeed.c.
- Deleted aspeed_eeprom.h and aspeed_eeprom.c; their FRUID data and
length definitions are now handled directly in the new Rainier file.
- Added aspeed_ast2600_rainier.c to the Meson build system (meson.build).
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed_eeprom.h | 15 ---
hw/arm/aspeed.c | 132 ---------------------
hw/arm/aspeed_ast2600_rainier.c | 197 ++++++++++++++++++++++++++++++++
hw/arm/aspeed_eeprom.c | 54 ---------
hw/arm/meson.build | 2 +-
5 files changed, 198 insertions(+), 202 deletions(-)
delete mode 100644 hw/arm/aspeed_eeprom.h
create mode 100644 hw/arm/aspeed_ast2600_rainier.c
delete mode 100644 hw/arm/aspeed_eeprom.c
diff --git a/hw/arm/aspeed_eeprom.h b/hw/arm/aspeed_eeprom.h
deleted file mode 100644
index 86b97e4c6d..0000000000
--- a/hw/arm/aspeed_eeprom.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) Meta Platforms, Inc. and affiliates.
- *
- * SPDX-License-Identifier: GPL-2.0-only
- */
-
-#ifndef ASPEED_EEPROM_H
-#define ASPEED_EEPROM_H
-
-extern const uint8_t rainier_bb_fruid[];
-extern const size_t rainier_bb_fruid_len;
-extern const uint8_t rainier_bmc_fruid[];
-extern const size_t rainier_bmc_fruid_len;
-
-#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index f508280050..36c3daa903 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -14,7 +14,6 @@
#include "hw/arm/boot.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
-#include "hw/arm/aspeed_eeprom.h"
#include "hw/block/flash.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
@@ -47,10 +46,6 @@ static struct arm_boot_info aspeed_board_binfo = {
#define AST2700_EVB_HW_STRAP2 0x00000700
#endif
-/* Rainier hardware value: (QEMU prototype) */
-#define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
-#define RAINIER_BMC_HW_STRAP2 0x80000848
-
#define AST_SMP_MAILBOX_BASE 0x1e6e2180
#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
@@ -299,110 +294,6 @@ I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
TYPE_PCA9554, addr);
}
-static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
- I2CSlave *i2c_mux;
-
- at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
-
- create_pca9552(soc, 3, 0x61);
-
- /* The rainier expects a TMP275 but a TMP105 is compatible */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
- 0x48);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
- 0x49);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
- 0x4a);
- i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
- "pca9546", 0x70);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
- create_pca9552(soc, 4, 0x60);
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
- 0x48);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
- 0x49);
- create_pca9552(soc, 5, 0x60);
- create_pca9552(soc, 5, 0x61);
- i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
- "pca9546", 0x70);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
- 0x48);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
- 0x4a);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
- 0x4b);
- i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
- "pca9546", 0x70);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
-
- create_pca9552(soc, 7, 0x30);
- create_pca9552(soc, 7, 0x31);
- create_pca9552(soc, 7, 0x32);
- create_pca9552(soc, 7, 0x33);
- create_pca9552(soc, 7, 0x60);
- create_pca9552(soc, 7, 0x61);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
- /* Bus 7: TODO si7021-a20@20 */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
- 0x48);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
- at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
- at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
- 0x48);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
- 0x4a);
- at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
- 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
- at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
- 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
- create_pca9552(soc, 8, 0x60);
- create_pca9552(soc, 8, 0x61);
- /* Bus 8: ucd90320@11 */
- /* Bus 8: ucd90320@b */
- /* Bus 8: ucd90320@c */
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
- at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
- at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
-
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
- 0x48);
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
- 0x49);
- i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
- "pca9546", 0x70);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
- create_pca9552(soc, 11, 0x60);
-
-
- at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
- create_pca9552(soc, 13, 0x60);
-
- at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
- create_pca9552(soc, 14, 0x60);
-
- at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
- create_pca9552(soc, 15, 0x60);
-}
-
#define TYPE_LM75 TYPE_TMP105
#define TYPE_TMP75 TYPE_TMP105
#define TYPE_TMP421 "tmp421"
@@ -759,25 +650,6 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
aspeed_machine_ast2600_class_emmc_init(oc);
};
-static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "IBM Rainier BMC (Cortex-A7)";
- amc->soc_name = "ast2600-a3";
- amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
- amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
- amc->fmc_model = "mx66l1g45g";
- amc->spi_model = "mx66l1g45g";
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
- amc->i2c_init = rainier_bmc_i2c_init;
- mc->default_ram_size = 1 * GiB;
- aspeed_machine_class_init_cpus_defaults(mc);
- aspeed_machine_ast2600_class_emmc_init(oc);
-};
-
static void aspeed_machine_catalina_class_init(ObjectClass *oc,
const void *data)
{
@@ -937,10 +809,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("rainier-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_rainier_class_init,
}, {
.name = MACHINE_TYPE_NAME("catalina-bmc"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2600_rainier.c b/hw/arm/aspeed_ast2600_rainier.c
new file mode 100644
index 0000000000..e408e1fb22
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_rainier.c
@@ -0,0 +1,197 @@
+/*
+ * IBM Rainier
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/nvram/eeprom_at24c.h"
+#include "hw/i2c/i2c_mux_pca954x.h"
+#include "hw/sensor/tmp105.h"
+
+/* Rainier hardware value: (QEMU prototype) */
+#define RAINIER_BMC_HW_STRAP1 (0x00422016 | SCU_AST2600_HW_STRAP_BOOT_SRC_EMMC)
+#define RAINIER_BMC_HW_STRAP2 0x80000848
+
+static const uint8_t rainier_bb_fruid[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84,
+ 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02,
+ 0x01, 0x00, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0x00, 0x00, 0x37,
+ 0x00, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x52, 0x54,
+ 0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x38, 0x56, 0x49, 0x4e, 0x49,
+ 0x00, 0x00, 0x81, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x56, 0x53,
+ 0x59, 0x53, 0x00, 0x00, 0xbb, 0x00, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x56, 0x43, 0x45, 0x4e, 0x00, 0x00, 0xe2, 0x00, 0x27, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x56, 0x53, 0x42, 0x50, 0x00, 0x00, 0x09, 0x01, 0x19, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x01, 0x00, 0x00, 0x00, 0x36, 0x00,
+ 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e, 0x49, 0x44, 0x52, 0x04, 0x44, 0x45,
+ 0x53, 0x43, 0x48, 0x57, 0x02, 0x30, 0x31, 0x43, 0x43, 0x04, 0x33, 0x34,
+ 0x35, 0x36, 0x46, 0x4e, 0x04, 0x46, 0x52, 0x34, 0x39, 0x53, 0x4e, 0x04,
+ 0x53, 0x52, 0x31, 0x32, 0x50, 0x4e, 0x04, 0x50, 0x52, 0x39, 0x39, 0x50,
+ 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x52, 0x54,
+ 0x04, 0x56, 0x53, 0x59, 0x53, 0x53, 0x45, 0x07, 0x49, 0x42, 0x4d, 0x53,
+ 0x59, 0x53, 0x31, 0x54, 0x4d, 0x08, 0x32, 0x32, 0x32, 0x32, 0x2d, 0x32,
+ 0x32, 0x32, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
+ 0x00, 0x52, 0x54, 0x04, 0x56, 0x43, 0x45, 0x4e, 0x53, 0x45, 0x07, 0x31,
+ 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x46, 0x43, 0x08, 0x31, 0x31, 0x31,
+ 0x31, 0x2d, 0x31, 0x31, 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x15, 0x00, 0x52, 0x54, 0x04, 0x56, 0x53, 0x42, 0x50, 0x49,
+ 0x4d, 0x04, 0x50, 0x00, 0x10, 0x01, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00,
+ 0x00, 0x00,
+};
+static const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
+
+/* Rainier BMC FRU */
+static const uint8_t rainier_bmc_fruid[] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84,
+ 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02,
+ 0x01, 0x00, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0x00, 0x00, 0x37,
+ 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x52, 0x54,
+ 0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x0e, 0x56, 0x49, 0x4e, 0x49,
+ 0x00, 0x00, 0x57, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46,
+ 0x01, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e,
+ 0x49, 0x44, 0x52, 0x04, 0x44, 0x45, 0x53, 0x43, 0x48, 0x57, 0x02, 0x30,
+ 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+static const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
+
+static void rainier_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ I2CSlave *i2c_mux;
+
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 0), 0x51, 32 * KiB);
+
+ create_pca9552(soc, 3, 0x61);
+
+ /* The rainier expects a TMP275 but a TMP105 is compatible */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
+ 0x48);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
+ 0x49);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105,
+ 0x4a);
+ i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4),
+ "pca9546", 0x70);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x52, 64 * KiB);
+ create_pca9552(soc, 4, 0x60);
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
+ 0x48);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105,
+ 0x49);
+ create_pca9552(soc, 5, 0x60);
+ create_pca9552(soc, 5, 0x61);
+ i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5),
+ "pca9546", 0x70);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
+ 0x48);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
+ 0x4a);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105,
+ 0x4b);
+ i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6),
+ "pca9546", 0x70);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 2), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 3), 0x51, 64 * KiB);
+
+ create_pca9552(soc, 7, 0x30);
+ create_pca9552(soc, 7, 0x31);
+ create_pca9552(soc, 7, 0x32);
+ create_pca9552(soc, 7, 0x33);
+ create_pca9552(soc, 7, 0x60);
+ create_pca9552(soc, 7, 0x61);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "dps310", 0x76);
+ /* Bus 7: TODO si7021-a20@20 */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105,
+ 0x48);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "max31785", 0x52);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, 64 * KiB);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 7), 0x51, 64 * KiB);
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
+ 0x48);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105,
+ 0x4a);
+ at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x50,
+ 64 * KiB, rainier_bb_fruid, rainier_bb_fruid_len);
+ at24c_eeprom_init_rom(aspeed_i2c_get_bus(&soc->i2c, 8), 0x51,
+ 64 * KiB, rainier_bmc_fruid, rainier_bmc_fruid_len);
+ create_pca9552(soc, 8, 0x60);
+ create_pca9552(soc, 8, 0x61);
+ /* Bus 8: ucd90320@11 */
+ /* Bus 8: ucd90320@b */
+ /* Bus 8: ucd90320@c */
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 9), 0x50, 128 * KiB);
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d);
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 10), 0x50, 128 * KiB);
+
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
+ 0x48);
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105,
+ 0x49);
+ i2c_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11),
+ "pca9546", 0x70);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 0), 0x50, 64 * KiB);
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x51, 64 * KiB);
+ create_pca9552(soc, 11, 0x60);
+
+
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 13), 0x50, 64 * KiB);
+ create_pca9552(soc, 13, 0x60);
+
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 14), 0x50, 64 * KiB);
+ create_pca9552(soc, 14, 0x60);
+
+ at24c_eeprom_init(aspeed_i2c_get_bus(&soc->i2c, 15), 0x50, 64 * KiB);
+ create_pca9552(soc, 15, 0x60);
+}
+
+static void aspeed_machine_rainier_class_init(ObjectClass *oc, const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "IBM Rainier BMC (Cortex-A7)";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = RAINIER_BMC_HW_STRAP1;
+ amc->hw_strap2 = RAINIER_BMC_HW_STRAP2;
+ amc->fmc_model = "mx66l1g45g";
+ amc->spi_model = "mx66l1g45g";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON;
+ amc->i2c_init = rainier_bmc_i2c_init;
+ mc->default_ram_size = 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+ aspeed_machine_ast2600_class_emmc_init(oc);
+};
+
+static const TypeInfo aspeed_ast2600_rainier_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("rainier-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_rainier_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_rainier_types)
+
diff --git a/hw/arm/aspeed_eeprom.c b/hw/arm/aspeed_eeprom.c
deleted file mode 100644
index 85a2aa4036..0000000000
--- a/hw/arm/aspeed_eeprom.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) Meta Platforms, Inc. and affiliates.
- *
- * SPDX-License-Identifier: GPL-2.0-only
- */
-
-#include "qemu/osdep.h"
-#include "aspeed_eeprom.h"
-
-const uint8_t rainier_bb_fruid[] = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84,
- 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02,
- 0x01, 0x00, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0x00, 0x00, 0x37,
- 0x00, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x46, 0x00, 0x52, 0x54,
- 0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x38, 0x56, 0x49, 0x4e, 0x49,
- 0x00, 0x00, 0x81, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x56, 0x53,
- 0x59, 0x53, 0x00, 0x00, 0xbb, 0x00, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x56, 0x43, 0x45, 0x4e, 0x00, 0x00, 0xe2, 0x00, 0x27, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x56, 0x53, 0x42, 0x50, 0x00, 0x00, 0x09, 0x01, 0x19, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x01, 0x00, 0x00, 0x00, 0x36, 0x00,
- 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e, 0x49, 0x44, 0x52, 0x04, 0x44, 0x45,
- 0x53, 0x43, 0x48, 0x57, 0x02, 0x30, 0x31, 0x43, 0x43, 0x04, 0x33, 0x34,
- 0x35, 0x36, 0x46, 0x4e, 0x04, 0x46, 0x52, 0x34, 0x39, 0x53, 0x4e, 0x04,
- 0x53, 0x52, 0x31, 0x32, 0x50, 0x4e, 0x04, 0x50, 0x52, 0x39, 0x39, 0x50,
- 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x52, 0x54,
- 0x04, 0x56, 0x53, 0x59, 0x53, 0x53, 0x45, 0x07, 0x49, 0x42, 0x4d, 0x53,
- 0x59, 0x53, 0x31, 0x54, 0x4d, 0x08, 0x32, 0x32, 0x32, 0x32, 0x2d, 0x32,
- 0x32, 0x32, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23,
- 0x00, 0x52, 0x54, 0x04, 0x56, 0x43, 0x45, 0x4e, 0x53, 0x45, 0x07, 0x31,
- 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x46, 0x43, 0x08, 0x31, 0x31, 0x31,
- 0x31, 0x2d, 0x31, 0x31, 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x15, 0x00, 0x52, 0x54, 0x04, 0x56, 0x53, 0x42, 0x50, 0x49,
- 0x4d, 0x04, 0x50, 0x00, 0x10, 0x01, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00,
- 0x00, 0x00,
-};
-
-/* Rainier BMC FRU */
-const uint8_t rainier_bmc_fruid[] = {
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84,
- 0x28, 0x00, 0x52, 0x54, 0x04, 0x56, 0x48, 0x44, 0x52, 0x56, 0x44, 0x02,
- 0x01, 0x00, 0x50, 0x54, 0x0e, 0x56, 0x54, 0x4f, 0x43, 0x00, 0x00, 0x37,
- 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46, 0x08, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x52, 0x54,
- 0x04, 0x56, 0x54, 0x4f, 0x43, 0x50, 0x54, 0x0e, 0x56, 0x49, 0x4e, 0x49,
- 0x00, 0x00, 0x57, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x46,
- 0x01, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x52, 0x54, 0x04, 0x56, 0x49, 0x4e,
- 0x49, 0x44, 0x52, 0x04, 0x44, 0x45, 0x53, 0x43, 0x48, 0x57, 0x02, 0x30,
- 0x31, 0x50, 0x46, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
-};
-
-const size_t rainier_bb_fruid_len = sizeof(rainier_bb_fruid);
-const size_t rainier_bmc_fruid_len = sizeof(rainier_bmc_fruid);
-
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 5f6036fdb0..e81dad1ac4 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -63,8 +63,8 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_gb200nvl.c',
'aspeed_ast2600_qcom-dc-scm-v1.c',
'aspeed_ast2600_qcom-firework.c',
+ 'aspeed_ast2600_rainier.c',
'aspeed_ast10x0.c',
- 'aspeed_eeprom.c',
'fby35.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast27x0.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 13/17] hw/arm/aspeed: Split Catalina machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (11 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 12/17] hw/arm/aspeed: Split Rainier " Jamin Lin via
@ 2025-10-29 4:36 ` Jamin Lin via
2025-10-29 4:37 ` [PATCH v2 14/17] hw/arm/aspeed: Split AST2600 EVB " Jamin Lin via
` (3 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:36 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Facebook Catalina BMC machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_catalina.c.
This refactor continues the ongoing modularization of Aspeed platform
support, organizing each board’s logic into its own dedicated source file.
It improves maintainability, readability, and simplifies future
development of new BMC platforms without cluttering aspeed.c.
Key updates include:
- Moved CATALINA_BMC_HW_STRAP1 and CATALINA_BMC_HW_STRAP2 macro definitions
into the new file.
- Moved catalina_bmc_i2c_init() and all Catalina-specific I2C device setup
into the new aspeed_ast2600_catalina.c file.
- Moved aspeed_machine_catalina_class_init() and type registration logic
out of aspeed.c.
- Cleaned up all Catalina-specific code and macros from aspeed.c.
- Added aspeed_ast2600_catalina.c to the Meson build system (meson.build).
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 204 ----------------------------
hw/arm/aspeed_ast2600_catalina.c | 224 +++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 225 insertions(+), 204 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_catalina.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 36c3daa903..81099e56b5 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -15,11 +15,9 @@
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/block/flash.h"
-#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
#include "hw/gpio/pca9552.h"
#include "hw/gpio/pca9554.h"
-#include "hw/nvram/eeprom_at24c.h"
#include "hw/sensor/tmp105.h"
#include "hw/misc/led.h"
#include "hw/qdev-properties.h"
@@ -294,184 +292,6 @@ I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr)
TYPE_PCA9554, addr);
}
-#define TYPE_LM75 TYPE_TMP105
-#define TYPE_TMP75 TYPE_TMP105
-#define TYPE_TMP421 "tmp421"
-#define TYPE_DS1338 "ds1338"
-
-/* Catalina hardware value */
-#define CATALINA_BMC_HW_STRAP1 0x00002002
-#define CATALINA_BMC_HW_STRAP2 0x00000800
-
-#define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
-
-static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
-{
- /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */
-
- AspeedSoCState *soc = bmc->soc;
- I2CBus *i2c[16] = {};
- I2CSlave *i2c_mux;
-
- /* busses 0-15 are all used. */
- for (int i = 0; i < ARRAY_SIZE(i2c); i++) {
- i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
- }
-
- /* &i2c0 */
- /* i2c-mux@71 (PCA9546) on i2c0 */
- i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71);
-
- /* i2c-mux@72 (PCA9546) on i2c0 */
- i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72);
-
- /* i2c0mux1ch1 */
- /* io_expander7 - pca9535@20 */
- i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
- TYPE_PCA9552, 0x20);
- /* eeprom@50 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB);
-
- /* i2c-mux@73 (PCA9546) on i2c0 */
- i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73);
-
- /* i2c-mux@75 (PCA9546) on i2c0 */
- i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75);
-
- /* i2c-mux@76 (PCA9546) on i2c0 */
- i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76);
-
- /* i2c0mux4ch1 */
- /* io_expander8 - pca9535@21 */
- i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
- TYPE_PCA9552, 0x21);
- /* eeprom@50 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB);
-
- /* i2c-mux@77 (PCA9546) on i2c0 */
- i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77);
-
-
- /* &i2c1 */
- /* i2c-mux@70 (PCA9548) on i2c1 */
- i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70);
- /* i2c1mux0ch0 */
- /* ina238@41 - no model */
- /* ina238@42 - no model */
- /* ina238@44 - no model */
- /* i2c1mux0ch1 */
- /* ina238@41 - no model */
- /* ina238@43 - no model */
- /* i2c1mux0ch4 */
- /* ltc4287@42 - no model */
- /* ltc4287@43 - no model */
-
- /* i2c1mux0ch5 */
- /* eeprom@54 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB);
- /* tpm75@4f */
- i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f);
-
- /* i2c1mux0ch6 */
- /* io_expander5 - pca9554@27 */
- i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
- TYPE_PCA9554, 0x27);
- /* io_expander6 - pca9555@25 */
- i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
- TYPE_PCA9552, 0x25);
- /* eeprom@51 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB);
-
- /* i2c1mux0ch7 */
- /* eeprom@53 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB);
- /* temperature-sensor@4b - tmp75 */
- i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b);
-
- /* &i2c2 */
- /* io_expander0 - pca9555@20 */
- i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20);
- /* io_expander0 - pca9555@21 */
- i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21);
- /* io_expander0 - pca9555@27 */
- i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27);
- /* eeprom@50 */
- at24c_eeprom_init(i2c[2], 0x50, 8 * KiB);
- /* eeprom@51 */
- at24c_eeprom_init(i2c[2], 0x51, 8 * KiB);
-
- /* &i2c5 */
- /* i2c-mux@70 (PCA9548) on i2c5 */
- i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70);
- /* i2c5mux0ch6 */
- /* eeprom@52 */
- at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB);
- /* i2c5mux0ch7 */
- /* ina230@40 - no model */
- /* ina230@41 - no model */
- /* ina230@44 - no model */
- /* ina230@45 - no model */
-
- /* &i2c6 */
- /* io_expander3 - pca9555@21 */
- i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21);
- /* rtc@6f - nct3018y */
- i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f);
-
- /* &i2c9 */
- /* io_expander4 - pca9555@4f */
- i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f);
- /* temperature-sensor@4b - tpm75 */
- i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b);
- /* eeprom@50 */
- at24c_eeprom_init(i2c[9], 0x50, 8 * KiB);
- /* eeprom@56 */
- at24c_eeprom_init(i2c[9], 0x56, 8 * KiB);
-
- /* &i2c10 */
- /* temperature-sensor@1f - tpm421 */
- i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f);
- /* eeprom@50 */
- at24c_eeprom_init(i2c[10], 0x50, 8 * KiB);
-
- /* &i2c11 */
- /* ssif-bmc@10 - no model */
-
- /* &i2c12 */
- /* eeprom@50 */
- at24c_eeprom_init(i2c[12], 0x50, 8 * KiB);
-
- /* &i2c13 */
- /* eeprom@50 */
- at24c_eeprom_init(i2c[13], 0x50, 8 * KiB);
- /* eeprom@54 */
- at24c_eeprom_init(i2c[13], 0x54, 256);
- /* eeprom@55 */
- at24c_eeprom_init(i2c[13], 0x55, 256);
- /* eeprom@57 */
- at24c_eeprom_init(i2c[13], 0x57, 256);
-
- /* &i2c14 */
- /* io_expander9 - pca9555@10 */
- i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10);
- /* io_expander10 - pca9555@11 */
- i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11);
- /* io_expander11 - pca9555@12 */
- i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12);
- /* io_expander12 - pca9555@13 */
- i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13);
- /* io_expander13 - pca9555@14 */
- i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14);
- /* io_expander14 - pca9555@15 */
- i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15);
-
- /* &i2c15 */
- /* temperature-sensor@1f - tmp421 */
- i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f);
- /* eeprom@52 */
- at24c_eeprom_init(i2c[15], 0x52, 8 * KiB);
-}
-
static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
{
return ASPEED_MACHINE(obj)->mmio_exec;
@@ -650,26 +470,6 @@ static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
aspeed_machine_ast2600_class_emmc_init(oc);
};
-static void aspeed_machine_catalina_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Facebook Catalina BMC (Cortex-A7)";
- amc->soc_name = "ast2600-a3";
- amc->hw_strap1 = CATALINA_BMC_HW_STRAP1;
- amc->hw_strap2 = CATALINA_BMC_HW_STRAP2;
- amc->fmc_model = "w25q01jvq";
- amc->spi_model = NULL;
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC2_ON;
- amc->i2c_init = catalina_bmc_i2c_init;
- mc->default_ram_size = CATALINA_BMC_RAM_SIZE;
- aspeed_machine_class_init_cpus_defaults(mc);
- aspeed_machine_ast2600_class_emmc_init(oc);
-}
-
#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
/* Main SYSCLK frequency in Hz (200MHz) */
#define SYSCLK_FRQ 200000000ULL
@@ -809,10 +609,6 @@ static const TypeInfo aspeed_machine_types[] = {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("catalina-bmc"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_catalina_class_init,
}, {
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catalina.c
new file mode 100644
index 0000000000..5a44bf9122
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_catalina.c
@@ -0,0 +1,224 @@
+/*
+ * Facebook Catalina
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/i2c/i2c_mux_pca954x.h"
+#include "hw/gpio/pca9552.h"
+#include "hw/gpio/pca9554.h"
+#include "hw/nvram/eeprom_at24c.h"
+#include "hw/sensor/tmp105.h"
+
+/* Catalina hardware value */
+#define CATALINA_BMC_HW_STRAP1 0x00002002
+#define CATALINA_BMC_HW_STRAP2 0x00000800
+#define CATALINA_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB)
+
+#define TYPE_TMP75 TYPE_TMP105
+#define TYPE_TMP421 "tmp421"
+#define TYPE_DS1338 "ds1338"
+
+static void catalina_bmc_i2c_init(AspeedMachineState *bmc)
+{
+ /* Reference from v6.16-rc2 aspeed-bmc-facebook-catalina.dts */
+
+ AspeedSoCState *soc = bmc->soc;
+ I2CBus *i2c[16] = {};
+ I2CSlave *i2c_mux;
+
+ /* busses 0-15 are all used. */
+ for (int i = 0; i < ARRAY_SIZE(i2c); i++) {
+ i2c[i] = aspeed_i2c_get_bus(&soc->i2c, i);
+ }
+
+ /* &i2c0 */
+ /* i2c-mux@71 (PCA9546) on i2c0 */
+ i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x71);
+
+ /* i2c-mux@72 (PCA9546) on i2c0 */
+ i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x72);
+
+ /* i2c0mux1ch1 */
+ /* io_expander7 - pca9535@20 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
+ TYPE_PCA9552, 0x20);
+ /* eeprom@50 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB);
+
+ /* i2c-mux@73 (PCA9546) on i2c0 */
+ i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x73);
+
+ /* i2c-mux@75 (PCA9546) on i2c0 */
+ i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x75);
+
+ /* i2c-mux@76 (PCA9546) on i2c0 */
+ i2c_mux = i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x76);
+
+ /* i2c0mux4ch1 */
+ /* io_expander8 - pca9535@21 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 1),
+ TYPE_PCA9552, 0x21);
+ /* eeprom@50 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 1), 0x50, 8 * KiB);
+
+ /* i2c-mux@77 (PCA9546) on i2c0 */
+ i2c_slave_create_simple(i2c[0], TYPE_PCA9546, 0x77);
+
+
+ /* &i2c1 */
+ /* i2c-mux@70 (PCA9548) on i2c1 */
+ i2c_mux = i2c_slave_create_simple(i2c[1], TYPE_PCA9548, 0x70);
+ /* i2c1mux0ch0 */
+ /* ina238@41 - no model */
+ /* ina238@42 - no model */
+ /* ina238@44 - no model */
+ /* i2c1mux0ch1 */
+ /* ina238@41 - no model */
+ /* ina238@43 - no model */
+ /* i2c1mux0ch4 */
+ /* ltc4287@42 - no model */
+ /* ltc4287@43 - no model */
+
+ /* i2c1mux0ch5 */
+ /* eeprom@54 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 5), 0x54, 8 * KiB);
+ /* tpm75@4f */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 5), TYPE_TMP75, 0x4f);
+
+ /* i2c1mux0ch6 */
+ /* io_expander5 - pca9554@27 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
+ TYPE_PCA9554, 0x27);
+ /* io_expander6 - pca9555@25 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 6),
+ TYPE_PCA9552, 0x25);
+ /* eeprom@51 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x51, 8 * KiB);
+
+ /* i2c1mux0ch7 */
+ /* eeprom@53 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 7), 0x53, 8 * KiB);
+ /* temperature-sensor@4b - tmp75 */
+ i2c_slave_create_simple(pca954x_i2c_get_bus(i2c_mux, 7), TYPE_TMP75, 0x4b);
+
+ /* &i2c2 */
+ /* io_expander0 - pca9555@20 */
+ i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x20);
+ /* io_expander0 - pca9555@21 */
+ i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x21);
+ /* io_expander0 - pca9555@27 */
+ i2c_slave_create_simple(i2c[2], TYPE_PCA9552, 0x27);
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[2], 0x50, 8 * KiB);
+ /* eeprom@51 */
+ at24c_eeprom_init(i2c[2], 0x51, 8 * KiB);
+
+ /* &i2c5 */
+ /* i2c-mux@70 (PCA9548) on i2c5 */
+ i2c_mux = i2c_slave_create_simple(i2c[5], TYPE_PCA9548, 0x70);
+ /* i2c5mux0ch6 */
+ /* eeprom@52 */
+ at24c_eeprom_init(pca954x_i2c_get_bus(i2c_mux, 6), 0x52, 8 * KiB);
+ /* i2c5mux0ch7 */
+ /* ina230@40 - no model */
+ /* ina230@41 - no model */
+ /* ina230@44 - no model */
+ /* ina230@45 - no model */
+
+ /* &i2c6 */
+ /* io_expander3 - pca9555@21 */
+ i2c_slave_create_simple(i2c[6], TYPE_PCA9552, 0x21);
+ /* rtc@6f - nct3018y */
+ i2c_slave_create_simple(i2c[6], TYPE_DS1338, 0x6f);
+
+ /* &i2c9 */
+ /* io_expander4 - pca9555@4f */
+ i2c_slave_create_simple(i2c[9], TYPE_PCA9552, 0x4f);
+ /* temperature-sensor@4b - tpm75 */
+ i2c_slave_create_simple(i2c[9], TYPE_TMP75, 0x4b);
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[9], 0x50, 8 * KiB);
+ /* eeprom@56 */
+ at24c_eeprom_init(i2c[9], 0x56, 8 * KiB);
+
+ /* &i2c10 */
+ /* temperature-sensor@1f - tpm421 */
+ i2c_slave_create_simple(i2c[10], TYPE_TMP421, 0x1f);
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[10], 0x50, 8 * KiB);
+
+ /* &i2c11 */
+ /* ssif-bmc@10 - no model */
+
+ /* &i2c12 */
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[12], 0x50, 8 * KiB);
+
+ /* &i2c13 */
+ /* eeprom@50 */
+ at24c_eeprom_init(i2c[13], 0x50, 8 * KiB);
+ /* eeprom@54 */
+ at24c_eeprom_init(i2c[13], 0x54, 256);
+ /* eeprom@55 */
+ at24c_eeprom_init(i2c[13], 0x55, 256);
+ /* eeprom@57 */
+ at24c_eeprom_init(i2c[13], 0x57, 256);
+
+ /* &i2c14 */
+ /* io_expander9 - pca9555@10 */
+ i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x10);
+ /* io_expander10 - pca9555@11 */
+ i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x11);
+ /* io_expander11 - pca9555@12 */
+ i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x12);
+ /* io_expander12 - pca9555@13 */
+ i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x13);
+ /* io_expander13 - pca9555@14 */
+ i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x14);
+ /* io_expander14 - pca9555@15 */
+ i2c_slave_create_simple(i2c[14], TYPE_PCA9552, 0x15);
+
+ /* &i2c15 */
+ /* temperature-sensor@1f - tmp421 */
+ i2c_slave_create_simple(i2c[15], TYPE_TMP421, 0x1f);
+ /* eeprom@52 */
+ at24c_eeprom_init(i2c[15], 0x52, 8 * KiB);
+}
+
+static void aspeed_machine_catalina_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Facebook Catalina BMC (Cortex-A7)";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = CATALINA_BMC_HW_STRAP1;
+ amc->hw_strap2 = CATALINA_BMC_HW_STRAP2;
+ amc->fmc_model = "w25q01jvq";
+ amc->spi_model = NULL;
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC2_ON;
+ amc->i2c_init = catalina_bmc_i2c_init;
+ mc->default_ram_size = CATALINA_BMC_RAM_SIZE;
+ aspeed_machine_class_init_cpus_defaults(mc);
+ aspeed_machine_ast2600_class_emmc_init(oc);
+}
+
+static const TypeInfo aspeed_ast2600_catalina_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("catalina-bmc"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_catalina_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_catalina_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index e81dad1ac4..75d25626d1 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -58,6 +58,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2500_yosemitev2.c',
'aspeed_ast2600.c',
'aspeed_ast2600_bletchley.c',
+ 'aspeed_ast2600_catalina.c',
'aspeed_ast2600_fby35.c',
'aspeed_ast2600_fuji.c',
'aspeed_ast2600_gb200nvl.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 14/17] hw/arm/aspeed: Split AST2600 EVB machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (12 preceding siblings ...)
2025-10-29 4:36 ` [PATCH v2 13/17] hw/arm/aspeed: Split Catalina " Jamin Lin via
@ 2025-10-29 4:37 ` Jamin Lin via
2025-10-29 4:37 ` [PATCH v2 15/17] hw/arm/aspeed: Split AST2700 " Jamin Lin via
` (2 subsequent siblings)
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:37 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Aspeed AST2600 EVB machine implementation out of
aspeed.c into a new standalone file aspeed_ast2600_evb.c.
This refactor continues the modularization effort of the Aspeed platform
machine definitions, separating each board’s initialization logic into its
own dedicated source file. It improves code maintainability, readability,
and reduces clutter in aspeed.c, simplifying future platform extensions.
Key updates include:
- Removed AST2600_EVB_HW_STRAP1 and AST2600_EVB_HW_STRAP2 macro definitions.
- Moved ast2600_evb_i2c_init() and related device initialization code into
the new aspeed_ast2600_evb.c file.
- Moved aspeed_machine_ast2600_evb_class_init() and type registration logic
out of aspeed.c.
- Added aspeed_ast2600_evb.c to the Meson build system (meson.build).
- Cleaned up all AST2600 EVB-specific code and macros from aspeed.c.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 43 -------------------------
hw/arm/aspeed_ast2600_evb.c | 64 +++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 65 insertions(+), 43 deletions(-)
create mode 100644 hw/arm/aspeed_ast2600_evb.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 81099e56b5..74d35021db 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -32,10 +32,6 @@ static struct arm_boot_info aspeed_board_binfo = {
.board_id = -1, /* device-tree-only board */
};
-/* AST2600 evb hardware value */
-#define AST2600_EVB_HW_STRAP1 0x000000C0
-#define AST2600_EVB_HW_STRAP2 0x00000003
-
#ifdef TARGET_AARCH64
/* AST2700 evb hardware value */
/* SCU HW Strap1 */
@@ -267,19 +263,6 @@ static void aspeed_machine_init(MachineState *machine)
arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
}
-static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
- uint8_t *eeprom_buf = g_malloc0(8 * 1024);
-
- smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
- eeprom_buf);
-
- /* LM75 is compatible with TMP105 driver */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
- TYPE_TMP105, 0x4d);
-}
-
void create_pca9552(AspeedSoCState *soc, int bus_id, int addr)
{
i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, bus_id),
@@ -448,28 +431,6 @@ static void aspeed_machine_class_init(ObjectClass *oc, const void *data)
aspeed_machine_class_props_init(oc);
}
-static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
- amc->soc_name = "ast2600-a3";
- amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
- amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
- amc->fmc_model = "w25q512jv";
- amc->spi_model = "w25q512jv";
- amc->num_cs = 1;
- amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
- ASPEED_MAC3_ON;
- amc->sdhci_wp_inverted = true;
- amc->i2c_init = ast2600_evb_i2c_init;
- mc->default_ram_size = 1 * GiB;
- aspeed_machine_class_init_cpus_defaults(mc);
- aspeed_machine_ast2600_class_emmc_init(oc);
-};
-
#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
/* Main SYSCLK frequency in Hz (200MHz) */
#define SYSCLK_FRQ 200000000ULL
@@ -606,10 +567,6 @@ static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
static const TypeInfo aspeed_machine_types[] = {
{
- .name = MACHINE_TYPE_NAME("ast2600-evb"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_ast2600_evb_class_init,
- }, {
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
diff --git a/hw/arm/aspeed_ast2600_evb.c b/hw/arm/aspeed_ast2600_evb.c
new file mode 100644
index 0000000000..07c46b7826
--- /dev/null
+++ b/hw/arm/aspeed_ast2600_evb.c
@@ -0,0 +1,64 @@
+/*
+ * ASPEED AST2600 EVB
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/i2c/smbus_eeprom.h"
+#include "hw/sensor/tmp105.h"
+
+/* AST2600 evb hardware value */
+#define AST2600_EVB_HW_STRAP1 0x000000C0
+#define AST2600_EVB_HW_STRAP2 0x00000003
+
+static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+ uint8_t *eeprom_buf = g_malloc0(8 * 1024);
+
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50,
+ eeprom_buf);
+
+ /* LM75 is compatible with TMP105 driver */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8),
+ TYPE_TMP105, 0x4d);
+}
+
+static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST2600 EVB (Cortex-A7)";
+ amc->soc_name = "ast2600-a3";
+ amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
+ amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
+ amc->fmc_model = "w25q512jv";
+ amc->spi_model = "w25q512jv";
+ amc->num_cs = 1;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON |
+ ASPEED_MAC3_ON;
+ amc->sdhci_wp_inverted = true;
+ amc->i2c_init = ast2600_evb_i2c_init;
+ mc->default_ram_size = 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+ aspeed_machine_ast2600_class_emmc_init(oc);
+};
+
+static const TypeInfo aspeed_ast2600_evb_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("ast2600-evb"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_ast2600_evb_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast2600_evb_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 75d25626d1..c3c054b74e 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -59,6 +59,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600.c',
'aspeed_ast2600_bletchley.c',
'aspeed_ast2600_catalina.c',
+ 'aspeed_ast2600_evb.c',
'aspeed_ast2600_fby35.c',
'aspeed_ast2600_fuji.c',
'aspeed_ast2600_gb200nvl.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 15/17] hw/arm/aspeed: Split AST2700 EVB machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (13 preceding siblings ...)
2025-10-29 4:37 ` [PATCH v2 14/17] hw/arm/aspeed: Split AST2600 EVB " Jamin Lin via
@ 2025-10-29 4:37 ` Jamin Lin via
2025-10-29 4:37 ` [PATCH v2 16/17] hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine API Jamin Lin via
2025-10-29 4:37 ` [PATCH v2 17/17] hw/arm/aspeed: Split AST1030 EVB machine into a separate source file for maintainability Jamin Lin via
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:37 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Aspeed AST2700 EVB machine implementation out of
aspeed.c into a new standalone file aspeed_ast27x0_evb.c.
This refactor continues the ongoing modularization of Aspeed platform
support, organizing each board’s initialization logic into its own
dedicated source file. It improves maintainability, readability, and
makes it easier to extend or update individual platform support without
cluttering aspeed.c.
Key updates include:
- Removed AST2700_EVB_HW_STRAP1 and AST2700_EVB_HW_STRAP2 macro definitions.
- Moved ast2700_evb_i2c_init(), aspeed_machine_ast2700a0_evb_class_init(),
and aspeed_machine_ast2700a1_evb_class_init() into the new
aspeed_ast27x0_evb.c file.
- Removed the AST2700 EVB machine type registration from aspeed.c.
- Added aspeed_ast27x0_evb.c to the Meson build system (meson.build).
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 72 -------------------------------
hw/arm/aspeed_ast27x0_evb.c | 86 +++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 87 insertions(+), 72 deletions(-)
create mode 100644 hw/arm/aspeed_ast27x0_evb.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 74d35021db..fc37f48802 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -32,14 +32,6 @@ static struct arm_boot_info aspeed_board_binfo = {
.board_id = -1, /* device-tree-only board */
};
-#ifdef TARGET_AARCH64
-/* AST2700 evb hardware value */
-/* SCU HW Strap1 */
-#define AST2700_EVB_HW_STRAP1 0x00000800
-/* SCUIO HW Strap1 */
-#define AST2700_EVB_HW_STRAP2 0x00000700
-#endif
-
#define AST_SMP_MAILBOX_BASE 0x1e6e2180
#define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
#define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
@@ -511,75 +503,11 @@ static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
aspeed_machine_class_init_cpus_defaults(mc);
}
-#ifdef TARGET_AARCH64
-static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
-
- /* LM75 is compatible with TMP105 driver */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0),
- TYPE_TMP105, 0x4d);
-}
-
-static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)";
- amc->soc_name = "ast2700-a0";
- amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
- amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
- amc->fmc_model = "w25q01jvq";
- amc->spi_model = "w25q512jv";
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
- amc->uart_default = ASPEED_DEV_UART12;
- amc->i2c_init = ast2700_evb_i2c_init;
- amc->vbootrom = true;
- mc->default_ram_size = 1 * GiB;
- aspeed_machine_class_init_cpus_defaults(mc);
-}
-
-static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->alias = "ast2700-evb";
- mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
- amc->soc_name = "ast2700-a1";
- amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
- amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
- amc->fmc_model = "w25q01jvq";
- amc->spi_model = "w25q512jv";
- amc->num_cs = 2;
- amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
- amc->uart_default = ASPEED_DEV_UART12;
- amc->i2c_init = ast2700_evb_i2c_init;
- amc->vbootrom = true;
- mc->default_ram_size = 1 * GiB;
- aspeed_machine_class_init_cpus_defaults(mc);
-}
-#endif
-
static const TypeInfo aspeed_machine_types[] = {
{
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
-#ifdef TARGET_AARCH64
- }, {
- .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_ast2700a0_evb_class_init,
- }, {
- .name = MACHINE_TYPE_NAME("ast2700a1-evb"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_machine_ast2700a1_evb_class_init,
-#endif
}, {
.name = TYPE_ASPEED_MACHINE,
.parent = TYPE_MACHINE,
diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
new file mode 100644
index 0000000000..76cbe2caf0
--- /dev/null
+++ b/hw/arm/aspeed_ast27x0_evb.c
@@ -0,0 +1,86 @@
+/*
+ * ASPEED AST27x0 EVB
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/sensor/tmp105.h"
+
+/* AST2700 evb hardware value */
+/* SCU HW Strap1 */
+#define AST2700_EVB_HW_STRAP1 0x00000800
+/* SCUIO HW Strap1 */
+#define AST2700_EVB_HW_STRAP2 0x00000700
+
+static void ast2700_evb_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+
+ /* LM75 is compatible with TMP105 driver */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0),
+ TYPE_TMP105, 0x4d);
+}
+
+static void aspeed_machine_ast2700a0_evb_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST2700 A0 EVB (Cortex-A35)";
+ amc->soc_name = "ast2700-a0";
+ amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
+ amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
+ amc->fmc_model = "w25q01jvq";
+ amc->spi_model = "w25q512jv";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
+ amc->uart_default = ASPEED_DEV_UART12;
+ amc->i2c_init = ast2700_evb_i2c_init;
+ amc->vbootrom = true;
+ mc->default_ram_size = 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static void aspeed_machine_ast2700a1_evb_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->alias = "ast2700-evb";
+ mc->desc = "Aspeed AST2700 A1 EVB (Cortex-A35)";
+ amc->soc_name = "ast2700-a1";
+ amc->hw_strap1 = AST2700_EVB_HW_STRAP1;
+ amc->hw_strap2 = AST2700_EVB_HW_STRAP2;
+ amc->fmc_model = "w25q01jvq";
+ amc->spi_model = "w25q512jv";
+ amc->num_cs = 2;
+ amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON | ASPEED_MAC2_ON;
+ amc->uart_default = ASPEED_DEV_UART12;
+ amc->i2c_init = ast2700_evb_i2c_init;
+ amc->vbootrom = true;
+ mc->default_ram_size = 1 * GiB;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast27x0_evb_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("ast2700a0-evb"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_ast2700a0_evb_class_init,
+ }, {
+ .name = MACHINE_TYPE_NAME("ast2700a1-evb"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_machine_ast2700a1_evb_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast27x0_evb_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index c3c054b74e..8e568e21b5 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -70,6 +70,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'fby35.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast27x0.c',
+ 'aspeed_ast27x0_evb.c',
'aspeed_ast27x0-fc.c',
'aspeed_ast27x0-ssp.c',
'aspeed_ast27x0-tsp.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 16/17] hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine API
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (14 preceding siblings ...)
2025-10-29 4:37 ` [PATCH v2 15/17] hw/arm/aspeed: Split AST2700 " Jamin Lin via
@ 2025-10-29 4:37 ` Jamin Lin via
2025-10-29 17:33 ` [SPAM] " Cédric Le Goater
2025-10-29 4:37 ` [PATCH v2 17/17] hw/arm/aspeed: Split AST1030 EVB machine into a separate source file for maintainability Jamin Lin via
16 siblings, 1 reply; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:37 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit promotes connect_serial_hds_to_uarts() to a public Aspeed
machine API, allowing board-specific implementations to use it for
connecting serial host devices to the SoC UARTs.
Previously, this function was declared static within aspeed.c and used
only internally. Making this function a public API standardizes that
process and avoids code duplication.
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
include/hw/arm/aspeed.h | 1 +
hw/arm/aspeed.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
index 02f0ea5522..1546d2952f 100644
--- a/include/hw/arm/aspeed.h
+++ b/include/hw/arm/aspeed.h
@@ -70,5 +70,6 @@ void aspeed_machine_class_init_cpus_defaults(MachineClass *mc);
void create_pca9552(AspeedSoCState *soc, int bus_id, int addr);
I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr);
void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc);
+void connect_serial_hds_to_uarts(AspeedMachineState *bmc);
#endif
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index fc37f48802..c5e8a0608d 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -117,7 +117,7 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
&error_fatal);
}
-static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
+void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
{
AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
AspeedSoCState *s = bmc->soc;
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH v2 17/17] hw/arm/aspeed: Split AST1030 EVB machine into a separate source file for maintainability
2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
` (15 preceding siblings ...)
2025-10-29 4:37 ` [PATCH v2 16/17] hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine API Jamin Lin via
@ 2025-10-29 4:37 ` Jamin Lin via
16 siblings, 0 replies; 19+ messages in thread
From: Jamin Lin via @ 2025-10-29 4:37 UTC (permalink / raw)
To: Cédric Le Goater, Peter Maydell, Steven Lee, Troy Lee,
Andrew Jeffery, Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: jamin_lin, troy_lee, kane_chen
This commit moves the Aspeed AST1030 MiniBMC machine
implementation out of aspeed.c into a new standalone file
aspeed_ast10x0_evb.c.
This refactor continues the modularization effort for Aspeed platform
support, placing each board’s logic and initialization sequence in its
own dedicated source file. It improves maintainability, readability, and
makes it easier to extend support for additional AST10x0-based variants.
Key updates include:
- Moved aspeed_minibmc_machine_init() and
aspeed_minibmc_machine_ast1030_evb_class_init() from aspeed.c to
aspeed_ast10x0_evb.c.
- Moved ast1030_evb_i2c_init() and associated I2C setup code.
- Removed AST1030 EVB machine type registration from aspeed.c.
- Added aspeed_ast10x0_evb.c to the Meson build system (meson.build).
No functional changes.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/arm/aspeed.c | 89 ------------------------------
hw/arm/aspeed_ast10x0_evb.c | 107 ++++++++++++++++++++++++++++++++++++
hw/arm/meson.build | 1 +
3 files changed, 108 insertions(+), 89 deletions(-)
create mode 100644 hw/arm/aspeed_ast10x0_evb.c
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index c5e8a0608d..8bf32cb220 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -15,14 +15,9 @@
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/block/flash.h"
-#include "hw/i2c/smbus_eeprom.h"
#include "hw/gpio/pca9552.h"
#include "hw/gpio/pca9554.h"
-#include "hw/sensor/tmp105.h"
-#include "hw/misc/led.h"
-#include "hw/qdev-properties.h"
#include "system/block-backend.h"
-#include "system/reset.h"
#include "qemu/error-report.h"
#include "qemu/units.h"
#include "hw/qdev-clock.h"
@@ -423,92 +418,8 @@ static void aspeed_machine_class_init(ObjectClass *oc, const void *data)
aspeed_machine_class_props_init(oc);
}
-#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
-/* Main SYSCLK frequency in Hz (200MHz) */
-#define SYSCLK_FRQ 200000000ULL
-
-static void aspeed_minibmc_machine_init(MachineState *machine)
-{
- AspeedMachineState *bmc = ASPEED_MACHINE(machine);
- AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
- Clock *sysclk;
-
- sysclk = clock_new(OBJECT(machine), "SYSCLK");
- clock_set_hz(sysclk, SYSCLK_FRQ);
-
- bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
- object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
- object_unref(OBJECT(bmc->soc));
- qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
-
- object_property_set_link(OBJECT(bmc->soc), "memory",
- OBJECT(get_system_memory()), &error_abort);
- connect_serial_hds_to_uarts(bmc);
- qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
-
- if (defaults_enabled()) {
- aspeed_board_init_flashes(&bmc->soc->fmc,
- bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
- amc->num_cs,
- 0);
-
- aspeed_board_init_flashes(&bmc->soc->spi[0],
- bmc->spi_model ? bmc->spi_model : amc->spi_model,
- amc->num_cs, amc->num_cs);
-
- aspeed_board_init_flashes(&bmc->soc->spi[1],
- bmc->spi_model ? bmc->spi_model : amc->spi_model,
- amc->num_cs, (amc->num_cs * 2));
- }
-
- if (amc->i2c_init) {
- amc->i2c_init(bmc);
- }
-
- armv7m_load_kernel(ARM_CPU(first_cpu),
- machine->kernel_filename,
- 0,
- AST1030_INTERNAL_FLASH_SIZE);
-}
-
-static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
-{
- AspeedSoCState *soc = bmc->soc;
-
- /* U10 24C08 connects to SDA/SCL Group 1 by default */
- uint8_t *eeprom_buf = g_malloc0(32 * 1024);
- smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
-
- /* U11 LM75 connects to SDA/SCL Group 2 by default */
- i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
-}
-
-static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
- const void *data)
-{
- MachineClass *mc = MACHINE_CLASS(oc);
- AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
-
- mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
- amc->soc_name = "ast1030-a1";
- amc->hw_strap1 = 0;
- amc->hw_strap2 = 0;
- mc->init = aspeed_minibmc_machine_init;
- amc->i2c_init = ast1030_evb_i2c_init;
- mc->default_ram_size = 0;
- amc->fmc_model = "w25q80bl";
- amc->spi_model = "w25q256";
- amc->num_cs = 2;
- amc->macs_mask = 0;
- aspeed_machine_class_init_cpus_defaults(mc);
-}
-
static const TypeInfo aspeed_machine_types[] = {
{
- .name = MACHINE_TYPE_NAME("ast1030-evb"),
- .parent = TYPE_ASPEED_MACHINE,
- .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
- }, {
.name = TYPE_ASPEED_MACHINE,
.parent = TYPE_MACHINE,
.instance_size = sizeof(AspeedMachineState),
diff --git a/hw/arm/aspeed_ast10x0_evb.c b/hw/arm/aspeed_ast10x0_evb.c
new file mode 100644
index 0000000000..fb34a47dbd
--- /dev/null
+++ b/hw/arm/aspeed_ast10x0_evb.c
@@ -0,0 +1,107 @@
+/*
+ * ASPEED AST10x0 EVB
+ *
+ * Copyright (C) 2025 ASPEED Technology Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/arm/boot.h"
+#include "hw/arm/aspeed.h"
+#include "hw/arm/aspeed_soc.h"
+#include "hw/qdev-clock.h"
+#include "system/system.h"
+#include "hw/i2c/smbus_eeprom.h"
+
+#define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024)
+/* Main SYSCLK frequency in Hz (200MHz) */
+#define SYSCLK_FRQ 200000000ULL
+
+static void aspeed_minibmc_machine_init(MachineState *machine)
+{
+ AspeedMachineState *bmc = ASPEED_MACHINE(machine);
+ AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
+ Clock *sysclk;
+
+ sysclk = clock_new(OBJECT(machine), "SYSCLK");
+ clock_set_hz(sysclk, SYSCLK_FRQ);
+
+ bmc->soc = ASPEED_SOC(object_new(amc->soc_name));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(bmc->soc));
+ object_unref(OBJECT(bmc->soc));
+ qdev_connect_clock_in(DEVICE(bmc->soc), "sysclk", sysclk);
+
+ object_property_set_link(OBJECT(bmc->soc), "memory",
+ OBJECT(get_system_memory()), &error_abort);
+ connect_serial_hds_to_uarts(bmc);
+ qdev_realize(DEVICE(bmc->soc), NULL, &error_abort);
+
+ if (defaults_enabled()) {
+ aspeed_board_init_flashes(&bmc->soc->fmc,
+ bmc->fmc_model ? bmc->fmc_model : amc->fmc_model,
+ amc->num_cs,
+ 0);
+
+ aspeed_board_init_flashes(&bmc->soc->spi[0],
+ bmc->spi_model ? bmc->spi_model : amc->spi_model,
+ amc->num_cs, amc->num_cs);
+
+ aspeed_board_init_flashes(&bmc->soc->spi[1],
+ bmc->spi_model ? bmc->spi_model : amc->spi_model,
+ amc->num_cs, (amc->num_cs * 2));
+ }
+
+ if (amc->i2c_init) {
+ amc->i2c_init(bmc);
+ }
+
+ armv7m_load_kernel(ARM_CPU(first_cpu),
+ machine->kernel_filename,
+ 0,
+ AST1030_INTERNAL_FLASH_SIZE);
+}
+
+static void ast1030_evb_i2c_init(AspeedMachineState *bmc)
+{
+ AspeedSoCState *soc = bmc->soc;
+
+ /* U10 24C08 connects to SDA/SCL Group 1 by default */
+ uint8_t *eeprom_buf = g_malloc0(32 * 1024);
+ smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50, eeprom_buf);
+
+ /* U11 LM75 connects to SDA/SCL Group 2 by default */
+ i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4d);
+}
+
+static void aspeed_minibmc_machine_ast1030_evb_class_init(ObjectClass *oc,
+ const void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
+
+ mc->desc = "Aspeed AST1030 MiniBMC (Cortex-M4)";
+ amc->soc_name = "ast1030-a1";
+ amc->hw_strap1 = 0;
+ amc->hw_strap2 = 0;
+ mc->init = aspeed_minibmc_machine_init;
+ amc->i2c_init = ast1030_evb_i2c_init;
+ mc->default_ram_size = 0;
+ amc->fmc_model = "w25q80bl";
+ amc->spi_model = "w25q256";
+ amc->num_cs = 2;
+ amc->macs_mask = 0;
+ aspeed_machine_class_init_cpus_defaults(mc);
+}
+
+static const TypeInfo aspeed_ast10x0_evb_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("ast1030-evb"),
+ .parent = TYPE_ASPEED_MACHINE,
+ .class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
+ },
+};
+
+DEFINE_TYPES(aspeed_ast10x0_evb_types)
+
diff --git a/hw/arm/meson.build b/hw/arm/meson.build
index 8e568e21b5..f46f3a1c84 100644
--- a/hw/arm/meson.build
+++ b/hw/arm/meson.build
@@ -67,6 +67,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files(
'aspeed_ast2600_qcom-firework.c',
'aspeed_ast2600_rainier.c',
'aspeed_ast10x0.c',
+ 'aspeed_ast10x0_evb.c',
'fby35.c'))
arm_common_ss.add(when: ['CONFIG_ASPEED_SOC', 'TARGET_AARCH64'], if_true: files(
'aspeed_ast27x0.c',
--
2.43.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [SPAM] [PATCH v2 16/17] hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine API
2025-10-29 4:37 ` [PATCH v2 16/17] hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine API Jamin Lin via
@ 2025-10-29 17:33 ` Cédric Le Goater
0 siblings, 0 replies; 19+ messages in thread
From: Cédric Le Goater @ 2025-10-29 17:33 UTC (permalink / raw)
To: Jamin Lin, Peter Maydell, Steven Lee, Troy Lee, Andrew Jeffery,
Joel Stanley, open list:All patches CC here,
open list:ASPEED BMCs
Cc: troy_lee, kane_chen
On 10/29/25 05:37, Jamin Lin wrote:
> This commit promotes connect_serial_hds_to_uarts() to a public Aspeed
> machine API, allowing board-specific implementations to use it for
> connecting serial host devices to the SoC UARTs.
>
> Previously, this function was declared static within aspeed.c and used
> only internally. Making this function a public API standardizes that
> process and avoids code duplication.
>
> No functional changes.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> ---
> include/hw/arm/aspeed.h | 1 +
> hw/arm/aspeed.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
> index 02f0ea5522..1546d2952f 100644
> --- a/include/hw/arm/aspeed.h
> +++ b/include/hw/arm/aspeed.h
> @@ -70,5 +70,6 @@ void aspeed_machine_class_init_cpus_defaults(MachineClass *mc);
> void create_pca9552(AspeedSoCState *soc, int bus_id, int addr);
> I2CSlave *create_pca9554(AspeedSoCState *soc, int bus_id, int addr);
> void aspeed_machine_ast2600_class_emmc_init(ObjectClass *oc);
> +void connect_serial_hds_to_uarts(AspeedMachineState *bmc);
>
> #endif
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index fc37f48802..c5e8a0608d 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -117,7 +117,7 @@ static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo, bool emmc,
> &error_fatal);
> }
>
> -static void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
> +void connect_serial_hds_to_uarts(AspeedMachineState *bmc)
> {
> AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(bmc);
> AspeedSoCState *s = bmc->soc;
Please add an 'aspeed_' prefix and consider documentation.
Thanks,
C.
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2025-10-29 17:34 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz follow: Atom feed
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2025-10-29 4:36 [PATCH v2 00/17] Split AST2400, AST2600, AST2700 and AST1030 SoC machines into separate source files for maintainability Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 01/17] hw/arm/aspeed: Split Quanta-Q71L machine into a separate source file " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 02/17] hw/arm/aspeed: Split Supermicro X11 " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 03/17] hw/arm/aspeed: Split Palmetto " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 04/17] hw/arm/aspeed: Move ASPEED_RAM_SIZE() macro to common header for reuse Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 05/17] hw/arm/aspeed: Split Bletchley machine into a separate source file for maintainability Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 06/17] hw/arm/aspeed: Split FBY35 BMC " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 07/17] hw/arm/aspeed: Split Fuji " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 08/17] hw/arm/aspeed: Split QCOM Firework " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 09/17] hw/arm/aspeed: Split QCOM DC-SCM V1 " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 10/17] hw/arm/aspeed: Make aspeed_machine_ast2600_class_emmc_init() a common API for eMMC boot setup Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 11/17] hw/arm/aspeed: Split GB200NVL machine into a separate source file for maintainability Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 12/17] hw/arm/aspeed: Split Rainier " Jamin Lin via
2025-10-29 4:36 ` [PATCH v2 13/17] hw/arm/aspeed: Split Catalina " Jamin Lin via
2025-10-29 4:37 ` [PATCH v2 14/17] hw/arm/aspeed: Split AST2600 EVB " Jamin Lin via
2025-10-29 4:37 ` [PATCH v2 15/17] hw/arm/aspeed: Split AST2700 " Jamin Lin via
2025-10-29 4:37 ` [PATCH v2 16/17] hw/arm/aspeed: Promote connect_serial_hds_to_uarts() to public machine API Jamin Lin via
2025-10-29 17:33 ` [SPAM] " Cédric Le Goater
2025-10-29 4:37 ` [PATCH v2 17/17] hw/arm/aspeed: Split AST1030 EVB machine into a separate source file for maintainability Jamin Lin via
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