From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6416BCCF9E9 for ; Wed, 29 Oct 2025 04:40:39 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vDxxE-00080w-NE; Wed, 29 Oct 2025 00:38:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDxxB-0007w9-Ih; Wed, 29 Oct 2025 00:38:33 -0400 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vDxx1-0004M3-GL; Wed, 29 Oct 2025 00:38:33 -0400 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 29 Oct 2025 12:37:14 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 29 Oct 2025 12:37:14 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:All patches CC here" , "open list:ASPEED BMCs" CC: , , Subject: [PATCH v2 08/17] hw/arm/aspeed: Split QCOM Firework machine into a separate source file for maintainability Date: Wed, 29 Oct 2025 12:36:54 +0800 Message-ID: <20251029043710.1486573-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251029043710.1486573-1-jamin_lin@aspeedtech.com> References: <20251029043710.1486573-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This commit moves the QCOM Firework BMC machine implementation out of aspeed.c into a new standalone file aspeed_ast2600_qcom-firework.c. This refactor continues the modularization effort for Aspeed platform support, placing each board’s logic in its own dedicated source file. It improves maintainability, readability, and simplifies future development for new platforms without cluttering aspeed.c. Key updates include: - Removed qcom_dc_scm_firework_i2c_init() and its Firework-specific devices from aspeed.c. - Removed aspeed_machine_qcom_firework_class_init() and its type registration ("qcom-firework-bmc") from aspeed_machine_types[]. - Added new source file aspeed_ast2600_qcom-firework.c containing the Firework-specific initialization and machine class definition. - Updated hw/arm/meson.build to include aspeed_ast2600_qcom-firework.c. - Cleaned up all Firework-specific code from aspeed.c. - Renamed `QCOM_DC_SCM_V1_BMC_HW_STRAP1` to `QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP1` to avoid dependency conflicts with other QCOM DC-SCM machines. No functional changes. Signed-off-by: Jamin Lin --- hw/arm/aspeed.c | 56 ----------------- hw/arm/aspeed_ast2600_qcom-firework.c | 90 +++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 91 insertions(+), 56 deletions(-) create mode 100644 hw/arm/aspeed_ast2600_qcom-firework.c diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 1f35706050..8d02678659 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -634,38 +634,6 @@ static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); } -static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) -{ - AspeedSoCState *soc = bmc->soc; - I2CSlave *therm_mux, *cpuvr_mux; - - /* Create the generic DC-SCM hardware */ - qcom_dc_scm_bmc_i2c_init(bmc); - - /* Now create the Firework specific hardware */ - - /* I2C7 CPUVR MUX */ - cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), - "pca9546", 0x70); - i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); - i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); - i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); - i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); - - /* I2C8 Thermal Diodes*/ - therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), - "pca9548", 0x70); - i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); - i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); - i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); - i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); - i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); - - /* I2C9 Fan Controller (MAX31785) */ - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); - i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); -} - static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -1062,26 +1030,6 @@ static void aspeed_machine_qcom_dc_scm_v1_class_init(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); }; -static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, - const void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); - - mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; - mc->deprecation_reason = "use 'ast2600-evb' instead"; - amc->soc_name = "ast2600-a3"; - amc->hw_strap1 = QCOM_DC_SCM_V1_BMC_HW_STRAP1; - amc->hw_strap2 = QCOM_DC_SCM_V1_BMC_HW_STRAP2; - amc->fmc_model = "n25q512a"; - amc->spi_model = "n25q512a"; - amc->num_cs = 2; - amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; - amc->i2c_init = qcom_dc_scm_firework_i2c_init; - mc->default_ram_size = 1 * GiB; - aspeed_machine_class_init_cpus_defaults(mc); -}; - static const TypeInfo aspeed_machine_types[] = { { .name = MACHINE_TYPE_NAME("ast2600-evb"), @@ -1091,10 +1039,6 @@ static const TypeInfo aspeed_machine_types[] = { .name = MACHINE_TYPE_NAME("qcom-dc-scm-v1-bmc"), .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_qcom_dc_scm_v1_class_init, - }, { - .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), - .parent = TYPE_ASPEED_MACHINE, - .class_init = aspeed_machine_qcom_firework_class_init, }, { .name = MACHINE_TYPE_NAME("rainier-bmc"), .parent = TYPE_ASPEED_MACHINE, diff --git a/hw/arm/aspeed_ast2600_qcom-firework.c b/hw/arm/aspeed_ast2600_qcom-firework.c new file mode 100644 index 0000000000..c9cfccda1f --- /dev/null +++ b/hw/arm/aspeed_ast2600_qcom-firework.c @@ -0,0 +1,90 @@ +/* + * Qualcomm DC-SCM V1/Firework + * + * Copyright (C) 2025 ASPEED Technology Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/aspeed.h" +#include "hw/arm/aspeed_soc.h" +#include "hw/i2c/i2c_mux_pca954x.h" +#include "hw/sensor/tmp105.h" + +/* Qualcomm DC-SCM Firework hardware value */ +#define QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP1 0x00000000 +#define QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP2 0x00000041 + +#define TYPE_LM75 TYPE_TMP105 + +static void qcom_dc_scm_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = bmc->soc; + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 15), "tmp105", 0x4d); +} + +static void qcom_dc_scm_firework_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = bmc->soc; + I2CSlave *therm_mux, *cpuvr_mux; + + /* Create the generic DC-SCM hardware */ + qcom_dc_scm_bmc_i2c_init(bmc); + + /* Now create the Firework specific hardware */ + + /* I2C7 CPUVR MUX */ + cpuvr_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), + "pca9546", 0x70); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 0), "pca9548", 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 1), "pca9548", 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 2), "pca9548", 0x72); + i2c_slave_create_simple(pca954x_i2c_get_bus(cpuvr_mux, 3), "pca9548", 0x72); + + /* I2C8 Thermal Diodes*/ + therm_mux = i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), + "pca9548", 0x70); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 0), TYPE_LM75, 0x4C); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 1), TYPE_LM75, 0x4C); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 2), TYPE_LM75, 0x48); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 3), TYPE_LM75, 0x48); + i2c_slave_create_simple(pca954x_i2c_get_bus(therm_mux, 4), TYPE_LM75, 0x48); + + /* I2C9 Fan Controller (MAX31785) */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x52); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "max31785", 0x54); +} + +static void aspeed_machine_qcom_firework_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Qualcomm DC-SCM V1/Firework BMC (Cortex A7)"; + mc->deprecation_reason = "use 'ast2600-evb' instead"; + amc->soc_name = "ast2600-a3"; + amc->hw_strap1 = QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP1; + amc->hw_strap2 = QCOM_DC_SCM_FIREWORK_BMC_HW_STRAP2; + amc->fmc_model = "n25q512a"; + amc->spi_model = "n25q512a"; + amc->num_cs = 2; + amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->i2c_init = qcom_dc_scm_firework_i2c_init; + mc->default_ram_size = 1 * GiB; + aspeed_machine_class_init_cpus_defaults(mc); +}; + +static const TypeInfo aspeed_ast2600_qcom_firework_types[] = { + { + .name = MACHINE_TYPE_NAME("qcom-firework-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_qcom_firework_class_init, + }, +}; + +DEFINE_TYPES(aspeed_ast2600_qcom_firework_types) + diff --git a/hw/arm/meson.build b/hw/arm/meson.build index c22b692260..89d2f05bd2 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -60,6 +60,7 @@ arm_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( 'aspeed_ast2600_bletchley.c', 'aspeed_ast2600_fby35.c', 'aspeed_ast2600_fuji.c', + 'aspeed_ast2600_qcom-firework.c', 'aspeed_ast10x0.c', 'aspeed_eeprom.c', 'fby35.c')) -- 2.43.0