From: Sairaj Kodilkar <sarunkod@amd.com>
To: <mst@redhat.com>, <imammedo@redhat.com>, <anisinha@redhat.com>,
<marcel.apfelbaum@gmail.com>, <pbonzini@redhat.com>,
<richard.henderson@linaro.org>, <eduardo@habkost.net>,
<yi.l.liu@intel.com>, <eric.auger@redhat.com>,
<zhenzhong.duan@intel.com>, <cohuck@redhat.com>,
<qemu-devel@nongnu.org>, <alejandro.j.jimenez@oracle.com>,
<vasant.hegde@amd.com>, <suravee.suthikulpanit@amd.com>
Cc: Sairaj Kodilkar <sarunkod@amd.com>
Subject: [RFC PATCH 1/5] [DO NOT MERGE] linux-headers: Introduce struct iommu_hw_info_amd
Date: Wed, 29 Oct 2025 15:31:48 +0530 [thread overview]
Message-ID: <20251029100152.4807-2-sarunkod@amd.com> (raw)
In-Reply-To: <20251029100152.4807-1-sarunkod@amd.com>
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Sairaj Kodilkar <sarunkod@amd.com>
---
| 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
--git a/linux-headers/linux/iommufd.h b/linux-headers/linux/iommufd.h
index 2105a039551e..c5fcb0396a38 100644
--- a/linux-headers/linux/iommufd.h
+++ b/linux-headers/linux/iommufd.h
@@ -613,6 +613,24 @@ struct iommu_hw_info_tegra241_cmdqv {
__u8 __reserved;
};
+/* struct iommu_hw_info_amd - AMD IOMMU device info
+ *
+ * @efr : Value of AMD IOMMU Extended Feature Register (EFR)
+ * @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2)
+ *
+ * Please See description of these registers in the following sections of
+ * the AMD I/O Virtualization Technology (IOMMU) Specification.
+ * (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_IOMMU.pdf)
+ *
+ * - MMIO Offset 0030h IOMMU Extended Feature Register
+ * - MMIO Offset 01A0h IOMMU Extended Feature 2 Register
+ */
+struct iommu_hw_info_amd {
+ __aligned_u64 efr;
+ __aligned_u64 efr2;
+ __aligned_u64 control_register;
+};
+
/**
* enum iommu_hw_info_type - IOMMU Hardware Info Types
* @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware
@@ -622,6 +640,7 @@ struct iommu_hw_info_tegra241_cmdqv {
* @IOMMU_HW_INFO_TYPE_ARM_SMMUV3: ARM SMMUv3 iommu info type
* @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM
* SMMUv3) info type
+ * @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type
*/
enum iommu_hw_info_type {
IOMMU_HW_INFO_TYPE_NONE = 0,
@@ -629,6 +648,7 @@ enum iommu_hw_info_type {
IOMMU_HW_INFO_TYPE_INTEL_VTD = 1,
IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2,
IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3,
+ IOMMU_HW_INFO_TYPE_AMD = 4,
};
/**
--
2.34.1
next prev parent reply other threads:[~2025-10-29 10:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 10:01 [RFC PATCH 0/5] amd_iommu: support up to 2048 MSI vectors per IRT Sairaj Kodilkar
2025-10-29 10:01 ` Sairaj Kodilkar [this message]
2025-10-29 10:01 ` [RFC PATCH 2/5] vfio/iommufd: Add amd specific hardware info struct to vendor capability Sairaj Kodilkar
2025-10-29 10:01 ` [RFC PATCH 3/5] amd-iommu: Add support for set/unset IOMMU for VFIO PCI devices Sairaj Kodilkar
2025-10-29 10:06 ` [RFC PATCH 4/5] amd_iommu: Add support for extended feature register 2 Sairaj Kodilkar
2025-10-29 10:09 ` [RFC PATCH 5/5] amd_iommu: Add support for upto 2048 interrupts per IRT Sairaj Kodilkar
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