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Wed, 29 Oct 2025 08:50:59 -0700 (PDT) Received: from draig.lan ([185.126.160.19]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b6da1e2226fsm1058044766b.20.2025.10.29.08.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Oct 2025 08:50:54 -0700 (PDT) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id B879E60C1B; Wed, 29 Oct 2025 15:50:47 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: Julian Ganz , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 19/35] target/mips: call plugin trap callbacks Date: Wed, 29 Oct 2025 15:50:28 +0000 Message-ID: <20251029155045.257802-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251029155045.257802-1-alex.bennee@linaro.org> References: <20251029155045.257802-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=alex.bennee@linaro.org; helo=mail-ej1-x62b.google.com X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: Julian Ganz We recently introduced API for registering callbacks for trap related events as well as the corresponding hook functions. Due to differences between architectures, the latter need to be called from target specific code. This change places hooks for MIPS targets. We consider the exceptions NMI and EXT_INTERRUPT to be asynchronous interrupts rather than exceptions. Reviewed-by: Richard Henderson Acked-by: Philippe Mathieu-Daudé Signed-off-by: Julian Ganz Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20251027110344.2289945-20-alex.bennee@linaro.org> Signed-off-by: Alex Bennée diff --git a/target/mips/tcg/system/tlb_helper.c b/target/mips/tcg/system/tlb_helper.c index 1e8901556d6..566924b079e 100644 --- a/target/mips/tcg/system/tlb_helper.c +++ b/target/mips/tcg/system/tlb_helper.c @@ -18,6 +18,7 @@ */ #include "qemu/osdep.h" #include "qemu/bitops.h" +#include "qemu/plugin.h" #include "cpu.h" #include "internal.h" @@ -1034,6 +1035,7 @@ void mips_cpu_do_interrupt(CPUState *cs) bool update_badinstr = 0; target_ulong offset; int cause = -1; + uint64_t last_pc = env->active_tc.PC; if (qemu_loglevel_mask(CPU_LOG_INT) && cs->exception_index != EXCP_EXT_INTERRUPT) { @@ -1052,6 +1054,7 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index = EXCP_NONE; mips_semihosting(env); env->active_tc.PC += env->error_code; + qemu_plugin_vcpu_hostcall_cb(cs, last_pc); return; case EXCP_DSS: env->CP0_Debug |= 1 << CP0DB_DSS; @@ -1336,6 +1339,14 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, env->CP0_DEPC); } + switch (cs->exception_index) { + case EXCP_NMI: + case EXCP_EXT_INTERRUPT: + qemu_plugin_vcpu_interrupt_cb(cs, last_pc); + break; + default: + qemu_plugin_vcpu_exception_cb(cs, last_pc); + } cs->exception_index = EXCP_NONE; } -- 2.47.3