qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PULL 23/23] hw/riscv: Replace target_ulong uses
Date: Wed, 29 Oct 2025 22:40:00 +0100	[thread overview]
Message-ID: <20251029214001.99824-24-philmd@linaro.org> (raw)
In-Reply-To: <20251029214001.99824-1-philmd@linaro.org>

From: Anton Johansson <anjo@rev.ng>

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-ID: <20251027-feature-single-binary-hw-v1-v2-2-44478d589ae9@rev.ng>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 hw/riscv/riscv-iommu.c | 6 ++++--
 hw/riscv/riscv_hart.c  | 2 +-
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index b33c7fe3259..f8656ec04b1 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -26,6 +26,8 @@
 #include "migration/vmstate.h"
 #include "qapi/error.h"
 #include "qemu/timer.h"
+#include "qemu/target-info.h"
+#include "qemu/bitops.h"
 
 #include "cpu_bits.h"
 #include "riscv-iommu.h"
@@ -391,9 +393,9 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx,
             const uint64_t va_mask = (1ULL << va_len) - 1;
 
             if (pass == S_STAGE && va_len > 32) {
-                target_ulong mask, masked_msbs;
+                uint64_t mask, masked_msbs;
 
-                mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1;
+                mask = MAKE_64BIT_MASK(0, target_long_bits() - va_len + 1);
                 masked_msbs = (addr >> (va_len - 1)) & mask;
 
                 if (masked_msbs != 0 && masked_msbs != mask) {
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 4d51a93dd52..33cbc9873e6 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -94,7 +94,7 @@ static bool csr_qtest_callback(CharFrontend *chr, gchar **words)
         g_assert(rc == 0);
         csr_call(words[1], cpu, csr, &val);
 
-        qtest_sendf(chr, "OK 0 "TARGET_FMT_lx"\n", (target_ulong)val);
+        qtest_sendf(chr, "OK 0 %"PRIx64"\n", val);
 
         return true;
     }
-- 
2.51.0



  parent reply	other threads:[~2025-10-29 22:09 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-29 21:39 [PULL 00/23] Misc single binary patches for 2025-10-29 Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 01/23] hw/arm: Register TYPE_TARGET_ARM/AARCH64_MACHINE QOM interfaces Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 02/23] hw/core: Allow ARM/Aarch64 binaries to use the 'none' machine Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 03/23] hw/arm: Add DEFINE_MACHINE_ARM() / DEFINE_MACHINE_AARCH64() macros Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 04/23] hw/arm: Filter machine types for qemu-system-arm/aarch64 binaries Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 05/23] meson: Prepare to accept per-binary TargetInfo structure implementation Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 06/23] config/target: Implement per-binary TargetInfo structure (ARM, AARCH64) Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 07/23] hw/arm/virt: Register valid CPU types dynamically Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 08/23] hw/arm/virt: Check accelerator availability at runtime Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 09/23] qemu/target_info: Add target_arm() helper Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 10/23] qemu/target_info: Add target_aarch64() helper Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 11/23] qemu/target_info: Add target_base_arm() helper Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 12/23] hw/arm/virt: Replace TARGET_AARCH64 -> target_aarch64() Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 13/23] hw/arm/virt: Get default CPU type at runtime Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 14/23] hw/arm/sbsa-ref: Include missing 'cpu.h' header Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 15/23] hw/arm/sbsa-ref: Build only once Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 16/23] hw/arm/virt-acpi-build: Include missing 'cpu.h' header Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 17/23] hw/arm/virt-acpi-build: Build only once Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 18/23] hw/arm/virt: " Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 19/23] hw/arm/meson: Move Xen files to arm_common_ss[] Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 20/23] hw/xen: Use BITS_PER_BYTE & MAKE_64BIT_MASK() in req_size_bits() Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 21/23] hw/xen: Replace target_ulong by agnostic target_long_bits() Philippe Mathieu-Daudé
2025-10-29 21:39 ` [PULL 22/23] hw/xen: Build only once Philippe Mathieu-Daudé
2025-10-29 21:40 ` Philippe Mathieu-Daudé [this message]
2025-10-30 10:04 ` [PULL 00/23] Misc single binary patches for 2025-10-29 Philippe Mathieu-Daudé
2025-10-30 13:44   ` Philippe Mathieu-Daudé

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20251029214001.99824-24-philmd@linaro.org \
    --to=philmd@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).