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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Roman Bolshakov" <rbolshakov@ddn.com>,
	"Alexander Graf" <agraf@csgraf.de>,
	"Phil Dennis-Jordan" <phil@philjordan.eu>,
	qemu-arm@nongnu.org, "Paolo Bonzini" <pbonzini@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@linaro.org>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Akihiko Odaki" <odaki@rsg.ci.i.u-tokyo.ac.jp>,
	"Peter Collingbourne" <pcc@google.com>,
	"Cameron Esfahani" <dirty@apple.com>,
	"Mads Ynddal" <mads@ynddal.dk>,
	"Mohamed Mediouni" <mohamed@unpredictable.fr>
Subject: [PATCH v4 17/23] target/arm: Create GTimers *after* features finalized / accel realized
Date: Mon,  3 Nov 2025 11:10:26 +0100	[thread overview]
Message-ID: <20251103101034.59039-18-philmd@linaro.org> (raw)
In-Reply-To: <20251103101034.59039-1-philmd@linaro.org>

Call generic (including accelerator) cpu_realize() handlers
*before* setting @gt_cntfrq_hz default

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 65 ++++++++++++++++++++++++------------------------
 1 file changed, 33 insertions(+), 32 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 39292fb9bc1..b392374df98 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1636,26 +1636,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
         return;
     }
 
-    if (!cpu->gt_cntfrq_hz) {
-        /*
-         * 0 means "the board didn't set a value, use the default". (We also
-         * get here for the CONFIG_USER_ONLY case.)
-         * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
-         * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
-         * which gives a 16ns tick period.
-         *
-         * We will use the back-compat value:
-         *  - for QEMU CPU types added before we standardized on 1GHz
-         *  - for versioned machine types with a version of 9.0 or earlier
-         */
-        if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
-            cpu->backcompat_cntfrq) {
-            cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
-        } else {
-            cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
-        }
-    }
-
 #ifndef CONFIG_USER_ONLY
     /* The NVIC and M-profile CPU are two halves of a single piece of
      * hardware; trying to use one without the other is a command line
@@ -1702,7 +1682,40 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
             return;
         }
     }
+#endif
 
+    cpu_exec_realizefn(cs, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    arm_cpu_finalize_features(cpu, &local_err);
+    if (local_err != NULL) {
+        error_propagate(errp, local_err);
+        return;
+    }
+
+    if (!cpu->gt_cntfrq_hz) {
+        /*
+         * 0 means "the board didn't set a value, use the default". (We also
+         * get here for the CONFIG_USER_ONLY case.)
+         * ARMv8.6 and later CPUs architecturally must use a 1GHz timer; before
+         * that it was an IMPDEF choice, and QEMU initially picked 62.5MHz,
+         * which gives a 16ns tick period.
+         *
+         * We will use the back-compat value:
+         *  - for QEMU CPU types added before we standardized on 1GHz
+         *  - for versioned machine types with a version of 9.0 or earlier
+         */
+        if (arm_feature(env, ARM_FEATURE_BACKCOMPAT_CNTFRQ) ||
+            cpu->backcompat_cntfrq) {
+            cpu->gt_cntfrq_hz = GTIMER_BACKCOMPAT_HZ;
+        } else {
+            cpu->gt_cntfrq_hz = GTIMER_DEFAULT_HZ;
+        }
+    }
+#ifndef CONFIG_USER_ONLY
     {
         uint64_t scale = gt_cntfrq_period_ns(cpu);
 
@@ -1723,18 +1736,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 #endif
 
-    cpu_exec_realizefn(cs, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
-    arm_cpu_finalize_features(cpu, &local_err);
-    if (local_err != NULL) {
-        error_propagate(errp, local_err);
-        return;
-    }
-
 #ifdef CONFIG_USER_ONLY
     /*
      * User mode relies on IC IVAU instructions to catch modification of
-- 
2.51.0



  parent reply	other threads:[~2025-11-03 10:19 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03 10:10 [PATCH v4 00/23] target/arm/hvf: Consolidate Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 01/23] accel/hvf: Create hvf_protect_clean_range, hvf_unprotect_dirty_range Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 02/23] target/i386/hvf: Use host page alignment in ept_emulation_fault() Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 03/23] accel/hvf: Enforce host alignment in hv_vm_protect() Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 04/23] target/i386/hvf: Use hvf_unprotect_dirty_range Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 05/23] target/i386/hvf: Use address_space_translate in ept_emulation_fault Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 06/23] accel/hvf: Simplify hvf_log_* Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 07/23] accel/hvf: Move hvf_log_sync to hvf_log_clear Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 08/23] accel/hvf: Simplify hvf_set_phys_mem Philippe Mathieu-Daudé
2025-11-03 11:59   ` Akihiko Odaki
2025-11-03 10:10 ` [PATCH v4 09/23] accel/hvf: Drop hvf_slot and hvf_find_overlap_slot Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 10/23] accel/hvf: Remove mac_slots Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 11/23] target/arm/hvf: Implement dirty page tracking Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 12/23] accel/hvf: Skip WFI if CPU has work to do Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 13/23] accel/hvf: Implement WFI without using pselect() Philippe Mathieu-Daudé
2025-11-03 12:17   ` Akihiko Odaki
2025-11-03 10:10 ` [PATCH v4 14/23] accel/hvf: Have PSCI CPU_SUSPEND halt the vCPU Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 15/23] accel: Introduce AccelOpsClass::cpu_target_realize() hook Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 16/23] accel/hvf: Add hvf_arch_cpu_realize() stubs Philippe Mathieu-Daudé
2025-11-03 10:10 ` Philippe Mathieu-Daudé [this message]
2025-11-03 10:10 ` [PATCH v4 18/23] target/arm/hvf: Really set Generic Timer counter frequency Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 19/23] target/arm: Only allow disabling NEON when using TCG Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 20/23] accel/hvf: Introduce hvf_arch_cpu_synchronize_[pre/post]exec() hooks Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 21/23] target/i386/hvf: Flush vCPU registers once before vcpu_exec() loop Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 22/23] target/arm/hvf: " Philippe Mathieu-Daudé
2025-11-03 10:10 ` [PATCH v4 23/23] accel/hvf: Sync CNTV_CTL_EL0 & CNTV_CVAL_EL0 Philippe Mathieu-Daudé
2025-11-03 12:45   ` Akihiko Odaki

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