From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, philmd@linaro.org,
alistair.francis@wdc.com, palmer@dabbelt.com,
Anton Johansson <anjo@rev.ng>
Subject: [PATCH v5 14/25] target/riscv: Fix size of [m|s|vs]iselect fields
Date: Mon, 3 Nov 2025 18:11:57 +0100 [thread overview]
Message-ID: <20251103171208.24355-15-anjo@rev.ng> (raw)
In-Reply-To: <20251103171208.24355-1-anjo@rev.ng>
[m|s|vs]iselect are defined in version 20250508 of the privileged
specification to be XLEN in size, however QEMU only ever uses at most
16 bits of these fields, so fix them to 16. Update relevant function
arguments.
Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 6 +++---
target/riscv/csr.c | 32 ++++++++++++++++----------------
target/riscv/machine.c | 6 +++---
3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 5f051796f4..b35851cf4f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -343,8 +343,8 @@ struct CPUArchState {
uint8_t siprio[64];
/* AIA CSRs */
- target_ulong miselect;
- target_ulong siselect;
+ uint16_t miselect;
+ uint16_t siselect;
uint64_t mvien;
uint64_t mvip;
@@ -390,7 +390,7 @@ struct CPUArchState {
uint64_t vsatp;
/* AIA VS-mode CSRs */
- target_ulong vsiselect;
+ uint16_t vsiselect;
uint64_t mtval2;
uint64_t mtinst;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 1c6797ca8d..a29edbb369 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2398,7 +2398,7 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
target_ulong *val, target_ulong new_val,
target_ulong wr_mask)
{
- target_ulong *iselect;
+ uint16_t *iselect;
int ret;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
@@ -2441,18 +2441,18 @@ static RISCVException rmw_xiselect(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static bool xiselect_aia_range(target_ulong isel)
+static bool xiselect_aia_range(uint16_t isel)
{
return (ISELECT_IPRIO0 <= isel && isel <= ISELECT_IPRIO15) ||
(ISELECT_IMSIC_FIRST <= isel && isel <= ISELECT_IMSIC_LAST);
}
-static bool xiselect_cd_range(target_ulong isel)
+static bool xiselect_cd_range(uint16_t isel)
{
return (ISELECT_CD_FIRST <= isel && isel <= ISELECT_CD_LAST);
}
-static bool xiselect_ctr_range(int csrno, target_ulong isel)
+static bool xiselect_ctr_range(int csrno, uint16_t isel)
{
/* MIREG-MIREG6 for the range 0x200-0x2ff are not used by CTR. */
return CTR_ENTRIES_FIRST <= isel && isel <= CTR_ENTRIES_LAST &&
@@ -2460,7 +2460,7 @@ static bool xiselect_ctr_range(int csrno, target_ulong isel)
}
static int rmw_iprio(target_ulong xlen,
- target_ulong iselect, uint8_t *iprio,
+ uint16_t iselect, uint8_t *iprio,
target_ulong *val, target_ulong new_val,
target_ulong wr_mask, int ext_irq_no)
{
@@ -2504,7 +2504,7 @@ static int rmw_iprio(target_ulong xlen,
return 0;
}
-static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val,
+static int rmw_ctrsource(CPURISCVState *env, uint16_t isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
/*
@@ -2543,7 +2543,7 @@ static int rmw_ctrsource(CPURISCVState *env, int isel, target_ulong *val,
return 0;
}
-static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val,
+static int rmw_ctrtarget(CPURISCVState *env, uint16_t isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
/*
@@ -2582,7 +2582,7 @@ static int rmw_ctrtarget(CPURISCVState *env, int isel, target_ulong *val,
return 0;
}
-static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val,
+static int rmw_ctrdata(CPURISCVState *env, uint16_t isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
/*
@@ -2623,7 +2623,7 @@ static int rmw_ctrdata(CPURISCVState *env, int isel, target_ulong *val,
}
static RISCVException rmw_xireg_aia(CPURISCVState *env, int csrno,
- target_ulong isel, target_ulong *val,
+ uint16_t isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
bool virt = false, isel_reserved = false;
@@ -2703,12 +2703,12 @@ done:
}
static int rmw_xireg_cd(CPURISCVState *env, int csrno,
- target_ulong isel, target_ulong *val,
+ uint16_t isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
int ret = -EINVAL;
- int ctr_index = isel - ISELECT_CD_FIRST;
- int isel_hpm_start = ISELECT_CD_FIRST + 3;
+ uint16_t ctr_index = isel - ISELECT_CD_FIRST;
+ uint16_t isel_hpm_start = ISELECT_CD_FIRST + 3;
if (!riscv_cpu_cfg(env)->ext_smcdeleg || !riscv_cpu_cfg(env)->ext_ssccfg) {
ret = RISCV_EXCP_ILLEGAL_INST;
@@ -2775,7 +2775,7 @@ done:
}
static int rmw_xireg_ctr(CPURISCVState *env, int csrno,
- target_ulong isel, target_ulong *val,
+ uint16_t isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
if (!riscv_cpu_cfg(env)->ext_smctr && !riscv_cpu_cfg(env)->ext_ssctr) {
@@ -2803,7 +2803,7 @@ static int rmw_xireg_ctr(CPURISCVState *env, int csrno,
* extension using csrind should be implemented here.
*/
static int rmw_xireg_csrind(CPURISCVState *env, int csrno,
- target_ulong isel, target_ulong *val,
+ uint16_t isel, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
bool virt = csrno == CSR_VSIREG ? true : false;
@@ -2833,7 +2833,7 @@ static int rmw_xiregi(CPURISCVState *env, int csrno, target_ulong *val,
target_ulong new_val, target_ulong wr_mask)
{
int ret = -EINVAL;
- target_ulong isel;
+ uint16_t isel;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
if (ret != RISCV_EXCP_NONE) {
@@ -2864,7 +2864,7 @@ static RISCVException rmw_xireg(CPURISCVState *env, int csrno,
target_ulong wr_mask)
{
int ret = -EINVAL;
- target_ulong isel;
+ uint16_t isel;
ret = smstateen_acc_ok(env, 0, SMSTATEEN0_SVSLCT);
if (ret != RISCV_EXCP_NONE) {
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 8a8f5be8d6..376075b2bd 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -108,7 +108,7 @@ static const VMStateDescription vmstate_hyper = {
VMSTATE_UINT64(env.vscause, RISCVCPU),
VMSTATE_UINT64(env.vstval, RISCVCPU),
VMSTATE_UINT64(env.vsatp, RISCVCPU),
- VMSTATE_UINTTL(env.vsiselect, RISCVCPU),
+ VMSTATE_UINT16(env.vsiselect, RISCVCPU),
VMSTATE_UINT64(env.vsie, RISCVCPU),
VMSTATE_UINT64(env.mtval2, RISCVCPU),
@@ -467,8 +467,8 @@ const VMStateDescription vmstate_riscv_cpu = {
VMSTATE_UINT64(env.mepc, RISCVCPU),
VMSTATE_UINT64(env.mcause, RISCVCPU),
VMSTATE_UINT64(env.mtval, RISCVCPU),
- VMSTATE_UINTTL(env.miselect, RISCVCPU),
- VMSTATE_UINTTL(env.siselect, RISCVCPU),
+ VMSTATE_UINT16(env.miselect, RISCVCPU),
+ VMSTATE_UINT16(env.siselect, RISCVCPU),
VMSTATE_UINT32(env.scounteren, RISCVCPU),
VMSTATE_UINT32(env.mcounteren, RISCVCPU),
VMSTATE_UINT32(env.scountinhibit, RISCVCPU),
--
2.51.0
next prev parent reply other threads:[~2025-11-03 17:15 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-03 17:11 [PATCH v5 00/25] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 01/25] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 02/25] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 03/25] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 04/25] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 05/25] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 06/25] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 07/25] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 08/25] target/riscv: Fix size of retxh Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 09/25] target/riscv: Fix size of ssp Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 10/25] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 11/25] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 12/25] target/riscv: Fix size of priv Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 13/25] target/riscv: Fix size of gei fields Anton Johansson via
2025-11-03 17:11 ` Anton Johansson via [this message]
2025-11-03 17:11 ` [PATCH v5 15/25] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 16/25] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 17/25] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 18/25] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 19/25] target/riscv: Replace target_ulong in riscv_ctr_add_entry() Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 20/25] target/riscv: Fix size of trigger data Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 21/25] target/riscv: Fix size of mseccfg Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 22/25] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 23/25] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 24/25] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 25/25] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via
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