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From: Anton Johansson via <qemu-devel@nongnu.org>
To: qemu-devel@nongnu.org
Cc: pierrick.bouvier@linaro.org, philmd@linaro.org,
	alistair.francis@wdc.com, palmer@dabbelt.com,
	Anton Johansson <anjo@rev.ng>
Subject: [PATCH v5 19/25] target/riscv: Replace target_ulong in riscv_ctr_add_entry()
Date: Mon,  3 Nov 2025 18:12:02 +0100	[thread overview]
Message-ID: <20251103171208.24355-20-anjo@rev.ng> (raw)
In-Reply-To: <20251103171208.24355-1-anjo@rev.ng>

Widen to 64 bits in size to hold all relevant values.  Note: src and dst
arguments change from signed to unsigned but no functional change is
incurred.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/cpu.h        | 5 +++--
 target/riscv/cpu_helper.c | 5 +++--
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c2be30795a..ee4444f22d 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -662,8 +662,9 @@ RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit);
 void riscv_cpu_set_mode(CPURISCVState *env, privilege_mode_t newpriv,
                         bool virt_en);
 
-void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
-    enum CTRType type, privilege_mode_t prev_priv, bool prev_virt);
+void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst,
+                         enum CTRType type, privilege_mode_t prev_priv,
+                         bool prev_virt);
 void riscv_ctr_clear(CPURISCVState *env);
 
 void riscv_translate_init(void);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b102f15ac6..20ff05a4b2 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -926,8 +926,9 @@ static bool riscv_ctr_check_xte(CPURISCVState *env,
  *    entry = isel - CTR_ENTRIES_FIRST;
  *    idx = (sctrstatus.WRPTR - entry - 1) & (depth - 1);
  */
-void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst,
-    enum CTRType type, privilege_mode_t src_priv, bool src_virt)
+void riscv_ctr_add_entry(CPURISCVState *env, uint64_t src, uint64_t dst,
+                         enum CTRType type, privilege_mode_t src_priv,
+                         bool src_virt)
 {
     bool tgt_virt = env->virt_enabled;
     uint64_t src_mask = riscv_ctr_priv_to_mask(src_priv, src_virt);
-- 
2.51.0



  parent reply	other threads:[~2025-11-03 17:16 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-03 17:11 [PATCH v5 00/25] single-binary: Make riscv cpu.h target independent Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 01/25] target/riscv: Fix size of gpr and gprh Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 02/25] target/riscv: Fix size of vector CSRs Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 03/25] target/riscv: Fix size of pc, load_[val|res] Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 04/25] target/riscv: Fix size of frm and fflags Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 05/25] target/riscv: Fix size of badaddr and bins Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 06/25] target/riscv: Fix size of guest_phys_fault_addr Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 07/25] target/riscv: Fix size of priv_ver and vext_ver Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 08/25] target/riscv: Fix size of retxh Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 09/25] target/riscv: Fix size of ssp Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 10/25] target/riscv: Fix size of excp_uw2 Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 11/25] target/riscv: Fix size of sw_check_code Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 12/25] target/riscv: Fix size of priv Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 13/25] target/riscv: Fix size of gei fields Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 14/25] target/riscv: Fix size of [m|s|vs]iselect fields Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 15/25] target/riscv: Fix arguments to board IMSIC emulation callbacks Anton Johansson via
2025-11-03 17:11 ` [PATCH v5 16/25] target/riscv: Fix size of irq_overflow_left Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 17/25] target/riscv: Indent PMUFixedCtrState correctly Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 18/25] target/riscv: Replace target_ulong in riscv_cpu_get_trap_name() Anton Johansson via
2025-11-03 17:12 ` Anton Johansson via [this message]
2025-11-03 17:12 ` [PATCH v5 20/25] target/riscv: Fix size of trigger data Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 21/25] target/riscv: Fix size of mseccfg Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 22/25] target/riscv: Move debug.h include away from cpu.h Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 23/25] target/riscv: Move CSR declarations to separate csr.h header Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 24/25] target/riscv: Introduce externally facing CSR access functions Anton Johansson via
2025-11-03 17:12 ` [PATCH v5 25/25] target/riscv: Make pmp.h target_ulong agnostic Anton Johansson via

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