From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4BFA9CCF9F8 for ; Mon, 3 Nov 2025 17:14:18 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vFy4A-0000bV-J0; Mon, 03 Nov 2025 12:10:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFy45-0000aw-7b for qemu-devel@nongnu.org; Mon, 03 Nov 2025 12:09:57 -0500 Received: from rev.ng ([94.130.142.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vFy3m-0000tw-Qs for qemu-devel@nongnu.org; Mon, 03 Nov 2025 12:09:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=rev.ng; s=dkim; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe: List-Post:List-Owner:List-Archive:List-Unsubscribe:List-Unsubscribe-Post: List-Help; bh=25qOpz0IPQn7WWT7YwM8Q4jnwJo27QOlw8+jdalefsw=; b=WjSWUmialRO96dO Q5krrqmTUqX0KXlHzoq+YG5rAG/ojOVYPDm95lCf1bSC1jK5NDrUmcIUp0YLsRtRp4Bx20WQymENc bZwLl2WagLp+qgjaws4jtNzI63vgD/ib4wetW+4E/2W/p3nk0McRC9iTy5ltMKg62CYH84CEfz6EJ Mc=; To: qemu-devel@nongnu.org Cc: pierrick.bouvier@linaro.org, philmd@linaro.org, alistair.francis@wdc.com, palmer@dabbelt.com, Anton Johansson Subject: [PATCH v5 20/25] target/riscv: Fix size of trigger data Date: Mon, 3 Nov 2025 18:12:03 +0100 Message-ID: <20251103171208.24355-21-anjo@rev.ng> In-Reply-To: <20251103171208.24355-1-anjo@rev.ng> References: <20251103171208.24355-1-anjo@rev.ng> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=94.130.142.21; envelope-from=anjo@rev.ng; helo=rev.ng X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Anton Johansson From: Anton Johansson via Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org mcontext is at most 14 bits in size with the H extension, fix to 16 bits. trigger_cur indexes into tdata*[RV_MAX_TRIGGERS] which holds 2 elements, fix to 8 bits. This patch also adds a migration entry for mcontext which is used in tandem with other debug data that is already migrated. Note, the cpu/debug VMSTATE version is bumped, breaking migration from older versions. Signed-off-by: Anton Johansson Reviewed-by: Pierrick Bouvier Reviewed-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- target/riscv/cpu.h | 10 +++++----- target/riscv/machine.c | 13 +++++++------ 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ee4444f22d..153480846a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -467,11 +467,11 @@ struct CPUArchState { target_ulong mseccfg; /* trigger module */ - target_ulong trigger_cur; - target_ulong tdata1[RV_MAX_TRIGGERS]; - target_ulong tdata2[RV_MAX_TRIGGERS]; - target_ulong tdata3[RV_MAX_TRIGGERS]; - target_ulong mcontext; + uint16_t mcontext; + uint8_t trigger_cur; + uint64_t tdata1[RV_MAX_TRIGGERS]; + uint64_t tdata2[RV_MAX_TRIGGERS]; + uint64_t tdata3[RV_MAX_TRIGGERS]; struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 376075b2bd..c6ebb58882 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -239,15 +239,16 @@ static int debug_post_load(void *opaque, int version_id) static const VMStateDescription vmstate_debug = { .name = "cpu/debug", - .version_id = 2, - .minimum_version_id = 2, + .version_id = 3, + .minimum_version_id = 3, .needed = debug_needed, .post_load = debug_post_load, .fields = (const VMStateField[]) { - VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), - VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), - VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), - VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINT16(env.mcontext, RISCVCPU), + VMSTATE_UINT8(env.trigger_cur, RISCVCPU), + VMSTATE_UINT64_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINT64_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS), + VMSTATE_UINT64_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS), VMSTATE_END_OF_LIST() } }; -- 2.51.0