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From: Jamin Lin via <qemu-devel@nongnu.org>
To: "Cédric Le Goater" <clg@kaod.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Steven Lee" <steven_lee@aspeedtech.com>,
	"Troy Lee" <leetroy@gmail.com>,
	"Andrew Jeffery" <andrew@codeconstruct.com.au>,
	"Joel Stanley" <joel@jms.id.au>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Kevin Wolf" <kwolf@redhat.com>,
	"Hanna Reitz" <hreitz@redhat.com>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>,
	"open list:Block layer core" <qemu-block@nongnu.org>
Cc: <jamin_lin@aspeedtech.com>, <troy_lee@aspeedtech.com>,
	<kane_chen@aspeedtech.com>
Subject: [PATCH v1 03/12] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2600 and AST1030
Date: Thu, 6 Nov 2025 16:49:12 +0800	[thread overview]
Message-ID: <20251106084925.1253704-4-jamin_lin@aspeedtech.com> (raw)
In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com>

According to the design of the AST2600, it has a Silicon Revision ID
Register, specifically SCU004 and SCU014, to set the Revision ID for the
AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is
set to 0x05030303.

In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AST2600_A3_SILICON_REV" was used for SCU004, while "s->silicon_rev" was
used for SCU014. The value of "s->silicon_rev" is set by the SoC layer
via the "silicon-rev" property. This patch aligns both SCU004 and SCU014
to use "s->silicon_rev" for consistency and flexibility.

Similarly, the "aspeed_ast1030_scu_reset" function also used a fixed
revision constant ("AST1030_A1_SILICON_REV"). This change updates it to
use the same "s->silicon_rev" property, ensuring that both SoCs follow
a consistent and configurable revision handling mechanism.

Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
 hw/misc/aspeed_scu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index a0ab5eed8f..1f996d5398 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -841,7 +841,7 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev)
      * of actual revision. QEMU and Linux only support A1 onwards so this is
      * sufficient.
      */
-    s->regs[AST2600_SILICON_REV] = AST2600_A3_SILICON_REV;
+    s->regs[AST2600_SILICON_REV] = s->silicon_rev;
     s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
     s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
     s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
@@ -1137,7 +1137,7 @@ static void aspeed_ast1030_scu_reset(DeviceState *dev)
 
     memcpy(s->regs, asc->resets, asc->nr_regs * 4);
 
-    s->regs[AST2600_SILICON_REV] = AST1030_A1_SILICON_REV;
+    s->regs[AST2600_SILICON_REV] = s->silicon_rev;
     s->regs[AST2600_SILICON_REV2] = s->silicon_rev;
     s->regs[AST2600_HW_STRAP1] = s->hw_strap1;
     s->regs[AST2600_HW_STRAP2] = s->hw_strap2;
-- 
2.43.0



  parent reply	other threads:[~2025-11-06  8:51 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-06  8:49 [PATCH v1 00/12] hw/arm/aspeed: Add AST1060 SoC and EVB support Jamin Lin via
2025-11-06  8:49 ` [PATCH v1 01/12] hw/arm/aspeed: Fix missing SPI IRQ connection causing DMA interrupt failure Jamin Lin via
2025-11-07  7:57   ` Cédric Le Goater
2025-11-10  2:05     ` Jamin Lin
2025-11-10 10:17   ` Cédric Le Goater
2025-11-06  8:49 ` [PATCH v1 02/12] hw/block/m25p80: Add SFDP table for Winbond W25Q02JVM flash Jamin Lin via
2025-11-10 14:04   ` Cédric Le Goater
2025-11-06  8:49 ` Jamin Lin via [this message]
2025-11-10 14:04   ` [PATCH v1 03/12] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2600 and AST1030 Cédric Le Goater
2025-11-06  8:49 ` [PATCH v1 04/12] hhw/misc/aspeed_scu: Add AST1060 A2 silicon revision definition Jamin Lin via
2025-11-10 14:04   ` Cédric Le Goater
2025-11-06  8:49 ` [PATCH v1 05/12] hw/arm/aspeed_ast10x0: Add common init function for AST10x0 SoCs Jamin Lin via
2025-11-10 14:05   ` Cédric Le Goater
2025-11-06  8:49 ` [PATCH v1 06/12] hw/arm/aspeed_ast10x0: Add common realize " Jamin Lin via
2025-11-11 18:18   ` Cédric Le Goater
2025-11-06  8:49 ` [PATCH v1 07/12] hw/arm/aspeed_ast10x0: Pass SoC name to common init for AST10x0 family reuse Jamin Lin via
2025-11-11 18:19   ` Cédric Le Goater
2025-11-12  1:21     ` Jamin Lin
2025-11-06  8:49 ` [PATCH v1 08/12] hw/arm/aspeed_ast10x0: Add AST1060 SoC support Jamin Lin via
2025-11-10 14:58   ` Philippe Mathieu-Daudé
2025-11-11  5:16     ` Jamin Lin
2025-11-06  8:49 ` [PATCH v1 09/12] hw/arm/aspeed_ast10x0_evb: Add AST1060 EVB machine support Jamin Lin via
2025-11-11 18:20   ` Cédric Le Goater
2025-11-12  1:53     ` Jamin Lin
2025-11-06  8:49 ` [PATCH v1 10/12] tests/functional/arm/test_aspeed_ast1060: Add functional tests for Aspeed AST1060 SoC Jamin Lin via
2025-11-11 18:21   ` Cédric Le Goater
2025-11-06  8:49 ` [PATCH v1 11/12] docs/system/arm/aspeed: Update Aspeed and 2700 family boards list Jamin Lin via
2025-11-11 18:22   ` Cédric Le Goater
2025-11-12  1:55     ` Jamin Lin
2025-11-06  8:49 ` [PATCH v1 12/12] docs/system/arm/aspeed: Update Aspeed MiniBMC section to include AST1060 PFR processor Jamin Lin via
2025-11-11 18:24   ` Cédric Le Goater
2025-11-12  2:09     ` Jamin Lin

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