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From: Jon Kohler <jon@nutanix.com>
To: pbonzini@redhat.com, zhao1.liu@intel.com, qemu-devel@nongnu.org,
	pawan.kumar.gupta@linux.intel.com
Cc: Jon Kohler <jon@nutanix.com>
Subject: [PATCH 1/5] target/i386: Add MSR_IA32_ARCH_CAPABILITIES ITS_NO
Date: Thu,  6 Nov 2025 10:46:21 -0700	[thread overview]
Message-ID: <20251106174626.49930-2-jon@nutanix.com> (raw)
In-Reply-To: <20251106174626.49930-1-jon@nutanix.com>

Add bit definition for Indirect Target Selection (ITS_NO) bit 62, to
allow ITS_NO to be added directly to a CPU model in the future.

Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Jon Kohler <jon@nutanix.com>
---
 target/i386/cpu.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index cee1f692a1..93f466fb2b 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1245,6 +1245,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define MSR_ARCH_CAP_PBRSB_NO           (1U << 24)
 #define MSR_ARCH_CAP_GDS_NO             (1U << 26)
 #define MSR_ARCH_CAP_RFDS_NO            (1U << 27)
+#define MSR_ARCH_CAP_ITS_NO             (1U << 62)
 
 #define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
 
-- 
2.43.0



  reply	other threads:[~2025-11-06 17:06 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-06 17:46 [PATCH 0/5] target/i386: introduce ITS_NO to several models Jon Kohler
2025-11-06 17:46 ` Jon Kohler [this message]
2025-11-06 17:46 ` [PATCH 2/5] target/i386: introduce SapphireRapids-v5 to expose ITS_NO Jon Kohler
2025-11-06 17:46 ` [PATCH 3/5] target/i386: introduce GraniteRapids-v4 " Jon Kohler
2025-11-06 17:46 ` [PATCH 4/5] target/i386: introduce SierraForest-v4 " Jon Kohler
2025-11-06 17:46 ` [PATCH 5/5] target/i386: introduce ClearwaterForest-v2 " Jon Kohler

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