[PATCH 4/9] target/riscv: add the RISCVCPUTimeSrcIf interface

[Luc Michel <luc.michel@amd.com>]

Add the RISCVCPUTimeSrcIf QOM interface to the RISC-V target. This
interface aims at replacing the existing env->rdtime_fn callback in the
RISC-V CPU env. It allows to query the current number of ticks, and the
tick frequency.

Signed-off-by: Luc Michel <luc.michel@amd.com>
---
 target/riscv/cpu-qom.h     | 34 ++++++++++++++++++++++++++++++++++
 target/riscv/time_helper.h | 16 ++++++++++++++++
 target/riscv/time_helper.c | 13 +++++++++++++
 3 files changed, 63 insertions(+)

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index 75f4e434085..e5bc23b2ef5 100644
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -58,6 +58,40 @@
 #define TYPE_RISCV_CPU_XIANGSHAN_KMH    RISCV_CPU_TYPE_NAME("xiangshan-kunminghu")
 #define TYPE_RISCV_CPU_HOST             RISCV_CPU_TYPE_NAME("host")
 
 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
 
+#define TYPE_RISCV_CPU_TIME_SRC_IF "riscv-cpu-time-src-if"
+
+typedef struct RISCVCPUTimeSrcIfClass RISCVCPUTimeSrcIfClass;
+DECLARE_CLASS_CHECKERS(RISCVCPUTimeSrcIfClass, RISCV_CPU_TIME_SRC_IF,
+                       TYPE_RISCV_CPU_TIME_SRC_IF)
+#define RISCV_CPU_TIME_SRC_IF(obj) \
+        INTERFACE_CHECK(RISCVCPUTimeSrcIf, (obj), TYPE_RISCV_CPU_TIME_SRC_IF)
+
+typedef struct RISCVCPUTimeSrcIf RISCVCPUTimeSrcIf;
+
+/**
+ * RISCVCPUTimeSrcIf interface
+ *
+ * This interface is used by CPUs implementing the sstc extension. When the CPU
+ * implements this extension, it must have a time source to implement the sstc
+ * timers. Devices implementing this interface provide a monotonic tick counter
+ * and the associated tick frequency so that the CPU code can compute timer
+ * deadlines.
+ */
+struct RISCVCPUTimeSrcIfClass {
+    InterfaceClass parent_class;
+
+    /**
+     * get_ticks: get the current value of the free running counter associated
+     * with this time source.
+     */
+    uint64_t (*get_ticks)(RISCVCPUTimeSrcIf *);
+
+    /**
+     * get_tick_freq: get the tick frequency of this time source.
+     */
+    uint32_t (*get_tick_freq)(RISCVCPUTimeSrcIf *);
+};
+
 #endif /* RISCV_CPU_QOM_H */
diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h
index af1f634f890..b51fdd96570 100644
--- a/target/riscv/time_helper.h
+++ b/target/riscv/time_helper.h
@@ -26,6 +26,22 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
                                uint64_t timecmp, uint64_t delta,
                                uint32_t timer_irq);
 void riscv_timer_stce_changed(CPURISCVState *env, bool is_m_mode, bool enable);
 void riscv_timer_init(RISCVCPU *cpu);
 
+static inline uint64_t riscv_cpu_time_src_get_ticks(RISCVCPUTimeSrcIf *src)
+{
+    RISCVCPUTimeSrcIfClass *rctsc = RISCV_CPU_TIME_SRC_IF_GET_CLASS(src);
+
+    g_assert(rctsc->get_ticks != NULL);
+    return rctsc->get_ticks(src);
+}
+
+static inline uint32_t riscv_cpu_time_src_get_tick_freq(RISCVCPUTimeSrcIf *src)
+{
+    RISCVCPUTimeSrcIfClass *rctsc = RISCV_CPU_TIME_SRC_IF_GET_CLASS(src);
+
+    g_assert(rctsc->get_tick_freq != NULL);
+    return rctsc->get_tick_freq(src);
+}
+
 #endif
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index d2ec8a94166..dc0777607ab 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -198,5 +198,18 @@ void riscv_timer_init(RISCVCPU *cpu)
     env->stimecmp = 0;
 
     env->vstimer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_vstimer_cb, cpu);
     env->vstimecmp = 0;
 }
+
+static const TypeInfo riscv_cpu_time_src_if_info = {
+    .name = TYPE_RISCV_CPU_TIME_SRC_IF,
+    .parent = TYPE_INTERFACE,
+    .class_size = sizeof(RISCVCPUTimeSrcIfClass),
+};
+
+static void riscv_cpu_time_src_if_register_types(void)
+{
+    type_register_static(&riscv_cpu_time_src_if_info);
+}
+
+type_init(riscv_cpu_time_src_if_register_types)
-- 
2.51.0