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Tue, 11 Nov 2025 16:51:20 -0800 (PST) Received: from [10.0.0.22] ([185.213.193.149]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8823892a79fsm81445096d6.4.2025.11.11.16.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Nov 2025 16:51:20 -0800 (PST) From: Gabriel Brookman Date: Tue, 11 Nov 2025 19:50:52 -0500 Subject: [PATCH RFC 3/5] target/arm: add TCSO bitmasks to SCTLR MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251111-feat-mte4-v1-3-72ef5cf276f9@gmail.com> References: <20251111-feat-mte4-v1-0-72ef5cf276f9@gmail.com> In-Reply-To: <20251111-feat-mte4-v1-0-72ef5cf276f9@gmail.com> To: qemu-devel@nongnu.org Cc: Peter Maydell , Gustavo Romero , qemu-arm@nongnu.org, Gabriel Brookman X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762908676; l=1752; i=brookmangabriel@gmail.com; s=20251009; h=from:subject:message-id; bh=diZ9mUz1IQ4dvWZ2C/1aTcAm0Esme9Dx1H9yg3kKA/4=; b=r5fa684PEoey00HtYsRByLb2cVizA5nbHy8Q4vu6XYIGVFe8qgMYiC0AYV8T/af9UM8352pwI wVRcIPXgtn7DbicNIrrCMFYpQthtQ0h6Mr+MNmZmyC4qk1tmswk9QsZ X-Developer-Key: i=brookmangabriel@gmail.com; a=ed25519; pk=m9TtPDal6WzoHNnQiHHKf8dTrv3DUCPUUTujuo8vNrw= Received-SPF: pass client-ip=2607:f8b0:4864:20::f35; envelope-from=brookmangabriel@gmail.com; helo=mail-qv1-xf35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org These are the bitmasks used to control the FEAT_MTE_STORE_ONLY feature. They are now named and setting these fields of SCTLR is ignored if MTE is disabled, as per convention. Signed-off-by: Gabriel Brookman --- target/arm/cpu.h | 2 ++ target/arm/helper.c | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 39f2b2e54d..2c7c76777f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1424,6 +1424,8 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ #define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ #define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ +#define SCTLR_TSCO0 (1ULL << 58) /* FEAT_MTE_STORE_ONLY */ +#define SCTLR_TSCO (1ULL << 59) /* FEAT_MTE_STORE_ONLY */ #define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ #define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 27ebc6f29b..32fbb2e25d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3364,10 +3364,10 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, if (ri->state == ARM_CP_STATE_AA64 && !cpu_isar_feature(aa64_mte, cpu)) { if (ri->opc1 == 6) { /* SCTLR_EL3 */ - value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA); + value &= ~(SCTLR_ITFSB | SCTLR_TCF | SCTLR_ATA | SCTLR_TSCO); } else { value &= ~(SCTLR_ITFSB | SCTLR_TCF0 | SCTLR_TCF | - SCTLR_ATA0 | SCTLR_ATA); + SCTLR_ATA0 | SCTLR_ATA | SCTLR_TSCO | SCTLR_TSCO0); } } -- 2.51.2