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Iglesias" , YannickV , "Edgar E. Iglesias" Subject: [PATCH v4 06/15] hw/dma/zynq-devcfg: Simulate dummy PL reset Date: Tue, 11 Nov 2025 11:28:27 +0100 Message-ID: <20251111102836.212535-7-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org From: YannickV Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT should indicate that the reset is finished successfully. In order to add a MMIO-Device as part of the PL in the Zynq, the reset logic must succeed. The PCFG_INIT flag is now set when the PL reset is triggered by PCFG_PROG_B. Indicating the reset was successful. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 28b3cd2902..53bcf49140 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -49,6 +49,7 @@ REG32(CTRL, 0x00) FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */ + FIELD(CTRL, PCFG_PROG_B, 30, 1) FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlock */ FIELD(CTRL, PCAP_MODE, 26, 1) FIELD(CTRL, MULTIBOOT_EN, 24, 1) @@ -116,6 +117,7 @@ REG32(STATUS, 0x14) FIELD(STATUS, PSS_GTS_USR_B, 11, 1) FIELD(STATUS, PSS_FST_CFG_B, 10, 1) FIELD(STATUS, PSS_CFG_RESET_B, 5, 1) + FIELD(STATUS, PCFG_INIT, 4, 1) REG32(DMA_SRC_ADDR, 0x18) REG32(DMA_DST_ADDR, 0x1C) @@ -204,6 +206,13 @@ static uint64_t r_ctrl_pre_write(RegisterInfo *reg, uint64_t val) val |= lock_ctrl_map[i] & s->regs[R_CTRL]; } } + + if (FIELD_EX32(val, CTRL, PCFG_PROG_B)) { + s->regs[R_STATUS] |= R_STATUS_PCFG_INIT_MASK; + } else { + s->regs[R_STATUS] &= ~R_STATUS_PCFG_INIT_MASK; + } + return val; } -- 2.47.3