From: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
To: qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com
Subject: [PATCH v4 0/6] target/riscv: Implement Smsdid and Smmpt extension
Date: Wed, 12 Nov 2025 14:49:39 +0800 [thread overview]
Message-ID: <20251112064945.46533-1-zhiwei_liu@linux.alibaba.com> (raw)
This patch set introduces support for the RISC-V Smmpt (Supervisor
Memory-tracking and Protection Table) extension. Smmpt provides a
hardware mechanism for fine-grained memory protection, checked after
address translation, which is particularly useful for supervisor-level
sandboxing and security monitoring.
The rfc patch set:
https://mail.gnu.org/archive/html/qemu-riscv/2025-09/msg00216.html
v3->v4:
1. Add missing review tags.
v2->v3:
1. Fix build error in patch 2.
2. Rebase to master.
rfc->v2:
1. When ext_smmpt is false or BARE mode, make other fields in mmpt
CSR zero.
2. Add patch 5 to fix smrnmi ISA string order.
3. Fix patch 6 smmpt and smsdid ISA string order.
4. Make smmpt and smsdid experiment extensions.
5. Add review tags.
LIU Zhiwei (6):
target/riscv: Add basic definitions and CSRs for SMMPT
target/riscv: Implement core SMMPT lookup logic
target/riscv: Integrate SMMPT checks into MMU and TLB fill
target/riscv: Implement SMMPT fence instructions
target/riscv: Fix smrnmi isa alphabetical order
target/riscv: Enable SMMPT extension
target/riscv/cpu.c | 6 +-
target/riscv/cpu.h | 9 +-
target/riscv/cpu_bits.h | 27 ++
target/riscv/cpu_cfg_fields.h.inc | 2 +
target/riscv/cpu_helper.c | 81 +++++-
target/riscv/csr.c | 95 ++++++
target/riscv/insn32.decode | 2 +
.../riscv/insn_trans/trans_privileged.c.inc | 30 ++
target/riscv/meson.build | 1 +
target/riscv/pmp.h | 3 +
target/riscv/riscv_smmpt.c | 274 ++++++++++++++++++
target/riscv/riscv_smmpt.h | 36 +++
12 files changed, 560 insertions(+), 6 deletions(-)
create mode 100644 target/riscv/riscv_smmpt.c
create mode 100644 target/riscv/riscv_smmpt.h
--
2.25.1
next reply other threads:[~2025-11-12 6:51 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-12 6:49 LIU Zhiwei [this message]
2025-11-12 6:49 ` [PATCH v4 1/6] target/riscv: Add basic definitions and CSRs for SMMPT LIU Zhiwei
2025-11-12 6:49 ` [PATCH v4 2/6] target/riscv: Implement core SMMPT lookup logic LIU Zhiwei
2025-11-12 6:49 ` [PATCH v4 3/6] target/riscv: Integrate SMMPT checks into MMU and TLB fill LIU Zhiwei
2025-11-12 6:49 ` [PATCH v4 4/6] target/riscv: Implement SMMPT fence instructions LIU Zhiwei
2025-11-12 6:49 ` [PATCH v4 5/6] target/riscv: Fix smrnmi isa alphabetical order LIU Zhiwei
2025-11-12 6:49 ` [PATCH v4 6/6] target/riscv: Enable SMMPT extension LIU Zhiwei
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